Table of Contents
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Summary Tables of Changes
Stepping
Number
B0
X
BH1
X
BH2
X
BH3
X
BH4
X
BH5
X
BH6
X
BH7
X
BH8
X
BH9
X
BH10
X
BH11
X
BH12
X
BH13
X
BH14
X
BH15
X
BH16
X
BH17
X
BH18
X
BH19
X
BH20
Specification Update
Status
No Fix An xTPR Update Transaction Cycle, if Enabled, May be Issued to the FSB after
the Processor has Issued a Stop-Grant Special Cycle
No Fix The Processor May Report a #TS Instead of a #GP Fault
No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause
an Unexpected Interrupt
No Fix MOV To/From Debug Registers Causes Debug Exception
No Fix A Write to an APIC Register Sometimes May Appear to Have Not Occurred
No Fix Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address
Translations
No Fix Value for LBR/BTS/BTM will be Incorrect after an Exit from SMM
No Fix Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to
Partial Memory Update
No Fix A Thermal Interrupt is Not Generated when the Current Temperature is Invalid
No Fix Programming the Digital Thermal Sensor (DTS) Threshold May Cause
Unexpected Thermal Interrupts
No Fix Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
No Fix Fault on ENTER Instruction May Result in Unexpected Value on Stack Frame
No Fix With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP
Exception May Take Single Step Trap before Retirement of Instruction
No Fix An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV
SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating
Point Exception
No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher
Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack
No Fix BTS(Branch Trace Store) and PEBS(Precise Event Based Sampling) May Update
Memory outside the BTS/PEBS Buffer
No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled
No Fix Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected
Instruction Execution Results
No Fix A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E or
PDPTE
No Fix IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly
Description
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