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BH5
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
Problem:
With respect to the retirement of instructions, stores to the uncacheable memory
based APIC register space are handled in a non-synchronized way. For example if an
instruction that masks the interrupt flag, for example CLI, is executed soon after an
uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the
interrupt masking operation may take effect before the actual priority has been
lowered. This may cause interrupts whose priority is lower than the initial TPR, but
higher than the final TPR, to not be serviced until the interrupt enabled flag is finally
set, i.e. by STI instruction. Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may delay their
service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read after the
APIC register write. This will force the store to the APIC register before any
subsequent instructions are executed. No commercial operating system is known to be
impacted by this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH6
Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
Address Translations
Problem:
An external A20M# pin if enabled forces address bit-20 to be masked (forced to zero)
to emulates real-address mode address wraparound at 1 megabyte. However, if all of
the following conditions are met, address bit-20 may not be masked.
• paging is enabled
• a linear address has bit-20 set
• the address references a large page
• A20M# is enabled
Implication: When A20M# is enabled and an address references a large page the resulting
translated physical address may be incorrect. This erratum has not been observed
with any commercially available operating system.
Workaround: Operating systems should not allow A20M# to be enabled if the masking of address
bit-20 could be applied to an address that references a large page. A20M# is normally
only used with the first megabyte of memory.
Status:
For the steppings affected, see the Summary Tables of Changes.
16
Errata
Specification Update
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