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Errata
BH23
Performance Monitoring Event for Outstanding Bus Requests Ignores
AnyThread Bit
Problem:
The Performance Monitoring Event of Outstanding Bus Requests will ignore the
AnyThread bit (IA32_PERFEVTSEL0 MSR (186H)/ IA32_PERFEVTSEL1 MSR (187H) bit
[21]) and will instead always count all transactions across all logical processors, even
when AnyThread is clear.
Implication: The performance monitor count may be incorrect when counting only the current
logical processor's outstanding bus requests on a processor supporting Hyper-
Threading Technology.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH24
Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
Problem:
During the transition from real mode to protected mode, if an SMI (System
Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection
Enable, bit 0) and the first far JMP, the subsequent RSM (Resume from System
Management Mode) may cause the lower two bits of CS segment register to be
corrupted.
The corruption of the bottom two bits of the CS segment register will have no impact unless software
explicitly examines the CS segment register between enabling protected mode and the
first far JMP. Intel® 64 and IA-32 Architectures Software Developer's Manual Volume
3A: System Programming Guide, Part 1, in the section titled "Switching to Protected
Mode" recommends the far JMP immediately follows the write to CR0 to enable
protected mode. Intel has not observed this erratum with any commercially available
software.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH25
GP and Fixed Performance Monitoring Counters With AnyThread Bit
Set May Not Accurately Count Only OS or Only USR Events
Problem:
A fixed or GP (general purpose) performance counter with the AnyThread bit
(IA32_FIXED_CTR_CTRL_MSR (38DH) bit[2] for IA32_FIXED_CTR0, bit[6] for
IA32_FIXED_CTR1, bit [10] for IA32_FIXED_CTR2; IA32_PERFEVTSEL0 MSR (186H)/
IA32_PERFEVTSEL1 MSR (187H) bit [21]) set may not count correctly when counting
only OS (ring 0) events or only USR (ring>0) events. The counters will count correctly
if they are counting both OS and USR events or if the AnyThread bit is clear.
A performance monitor counter may be incorrect when it is counting for all logical processors on that
core and not counting at all privilege levels. This erratum will only occur on processors
supporting multiple logical processors per core.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
23
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