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Errata
BH7
Value for LBR/BTS/BTM will be Incorrect after an Exit from SMM
Problem:
After a return from SMM (System Management Mode), the CPU will incorrectly update
the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering
their data invalid. The corresponding data if sent out as a BTM on the system bus will
also be incorrect.
Note: This issue would only occur when one of the 3 above mentioned debug support
facilities are used.
Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not
be used.
Workaround: None.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH8
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
Problem:
A partial memory state save of the 512-byte FXSAVE image or a partial memory state
restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit
while the processor is operating in 16-bit mode or if a memory address exceeds the
4GB limit while the processor is operating in 32-bit mode.
Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected
but the memory state may be only partially saved or restored.
Workaround: Software should avoid memory accesses that wrap around the respective 16-bit and
32-bit mode memory limits.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH9
A Thermal Interrupt is Not Generated when the Current Temperature
is Invalid
Problem:
When the DTS (Digital Thermal Sensor) crosses one of its programmed thresholds it
generates an interrupt and logs the event (IA32_THERM_STATUS MSR (019Ch) bits
[9,7]). Due to this erratum, if the DTS reaches an invalid temperature (as indicated
IA32_THERM_STATUS MSR bit[31]) it does not generate an interrupt even if one of
the programmed thresholds is crossed and the corresponding log bits become set.
Implication: When the temperature reaches an invalid temperature the CPU does not generate a
Thermal interrupt even if a programmed threshold is crossed.
Workaround: None.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
17
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