Agp Timing Settings; Pci Timing Settings - JETWAY POLARIS400 User Manual

M/b for socket-a athlon/duron processor

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Table Of Contents

Table of Contents

AGP Transfer Aperture Size

AGP Transfer Mode

AGP Driving Control

AGP Driving Value

AGP Fast Write

AGP Master 1 WS Write

AGP Master 1 WS Read

CPU to AGP Post Write

AGP Delay Transaction

↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit

F5:Previous Values

Note: Change these settings only if you are familiar with the chipset.

3-6-3 PCI Timing Settings

PCI Master 1 WS Write

PCI Master 1 WS Read

CPU to AGP Post Write

PCI Delay Transaction

↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit

F5:Previous Values

PCI Delay Transaction

The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.

Select Enabled to support compliance with PCI specification version 2.1. The settings are:

Enabled and Disabled.

3-7 Integrated Peripherals