Agp Function Settings; Agp Timing Settings; Pci Timing Settings - JETWAY K8M8M - REV 3.0 User Manual

3-6-2 AGP Timing Settings

AGP Aperture Size
AGP Transfer Mode
AGP Driving Control
X AGP Driving Value
AGP Fast Write
AGP Master 1 WS Write
AGP Master 1 WS Read
CPU to AGP Post Write
AGP Delay Transaction
AGP 3.0 Calibration Cycle
VGA Share Memory Size
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
Note: Change these settings only if you are familiar with the chipset.

3-6-3 PCI Timing Settings

PCI Master 1 WS Write
PCI Master 1 WS Read
CPU to PCI Post Write
PCI Delay Transaction
VLink Data Rate
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
Phoenix – AwardBIOS CMOS Setup Utility
AGP Timing Settings
128M
8X
Auto
9A
Disabled
Disabled
Disabled
Enabled
Disabled
Enabled
64M
F6:Optimized Defaults
Phoenix – AwardBIOS CMOS Setup Utility
PCI Timing Settings
Disabled
Disabled
Enabled
Disabled
8X
F6:Optimized Defaults
Menu Level >>
F7:Standard Defaults
Menu Level >>
F7:Standard Defaults
25
Item Help
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Item Help
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