Dram Configuration - TYAN TOMCAT K8E Manual

3.8.1 DRAM Configuration

Timing Mode
Memclock index value (Mhz)
x CAS# latency (TCL)
x Min RAS# active time (Tras)
x RAS# to CAS# delay (Trcd)
x Row precharge Time (Trp)
1T/2T Memory Timing
S/W memory hole Romapping
H/W memory hole Remapping
MTRR mapping mode
DRAM ECC feature control
ECC memory Interlock
ECC MCE enable
Chip-Kill mode enable
ECC Redirection
DRAM background scrubber
DCache background scrubber
L2 cache background scrubb
Timing Mode
This option permits you to either manually select memory timings, or allow
the SPD (Serial Presence Detect) to determine the said timings automatically.
Auto / Manual
Memclock index value (Mhz)
This feature is used to set the Memclock index value.
100Mhz / 133Mhz / 166Mhz / 200Mhz
CAS# latency (TCL)
This setting controls the time delay (in clock cycles - CLKs) that passes
before the DRAM starts to carry out a read command after receiving it. This
also determines the number of CLKs for the completion of the first part of a
burst transfer. In other words, the lower the latency, the faster the
transaction.
2 / 2.5 / 3
Phoenix-AwardBIOS CMOS Setup Utility
DRAM Configuration
http://www.tyan.com
[Auto]
200Mhz
2.5
8T
4T
2T
2T
[Disabled]
[Enabled]
[Continuous]
[Enabled]
[At Least One]
[Enabled]
[Disabled]
[Enabled]
[Disabled]
[Disabled]
[Disabled]
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