Table of Contents
Advertisement
AGP & P2P Bridge Control
AGP Aperture Size
AGP3.0 Mode
AGP Driving Control
x AGP Driving Value
AGP Fast Write
AGP Master 1 WS Write
AGP Master 1 WS Read
AGP 3.0 Calibration cycle
VGA Share Memory Size
Direct Frame Buffer
Select Display Device
Panel Type
Outport Port
Dithering
TV-Layout
TV-type
TV-connector
: Move
Enter: Select
F5: Previous Values
CPU & PCI Bus Control
PCI Master 0 WS Write
PCI Delay Transaction
VLink mode selection
VLink 8x Support
DRDY_Timing
: Move
Enter: Select
F5: Previous Values
Current FSB Frequency
Detect front side bus automatically.
Current DRAM Frequency
Detect DRAM fruquency automatically.
DRAM Clock
By SPD
Set DRAM Clock by SPD.(Default Value)
200MHz
Set DRAM Clock to 200MHz.
266MHz
Set DRAM Clock to 266MHz.
333MHz
Set DRAM Clock to 333MHz.
GA-C7V7-RH Motherboard
Phoenix- AwardBIOS CMOS Setup Utility
AGP & P2P Bridge Control
[128M]
[8X]
[Auto]
DA
[Disabled]
[Enabled]
[Enabled]
[Disabled]
[64M]
[Enabled]
[CRT]
[07]
[DI0]
[Disabled]
[Default]
[NTSC]
[CVBS]
+/-/PU/PD: Value
F10: Save
F6: Fail-Safe Defaults
Phoenix- AwardBIOS CMOS Setup Utility
CPU & PCI Bus Control
[Enabled]
[Enabled]
[By Auto]
[Enabled]
[Default]
+/-/PU/PD: Value
F10: Save
F6: Fail-Safe Defaults
- 28 -
Item Help
Menu Level
ESC: Exit
F1: General Help
F7: Optimized Defaults
Item Help
Menu Level
ESC: Exit
F1: General Help
F7: Optimized Defaults
Advertisement
Table of Contents
