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RESET_B
Reset
PLL
Some MHz
Halt
to 68 MHz
Ctrl
PLLDIV[2:0]
PLL
XOUT
Oscillation
circuit
Oscillation
XIN/
SCANCK
ON/OFF
SCANCK
Current consumption
is decreased in a
standby mode.
BUFOFF_B
VideoDisplay IF
VDRD
DB[15:0]
Read Buffer
ReadDATA
6 bit x 4
RSP
RD_B
WriteDATA
WR_B
CPU system
buffer
CS_B
WAIT_B
LCDINT
Format conversion
circuit
HSWRD
HSEN
HSCK
Conversion from YUV
to RGB
HSD[7:0]
(Available for high-
speed pipelines)
Pallet gamma circuit
DCS_B
PalletRAM
DA[1:0]
Pallet
RAM(R)
EXCS_B[3:0]
8bitx256
RAM(G)
RAM(B)
RAM for BS mag/sol
For BS magnification function/
3D data sort function
LINE_Buffer (160 pixels x 48 x 4)
Buffer RAM for 1 line
Buffer RAM for 1 line
Buffer RAM for 1 line
Buffer RAM for 1 line
Bit Stream circuit A
BS_CLK
MCLK
phase
conversion
Buffer
control
creation
UV determination
and latch control
signal creation
H/V effective
STKCHK
signal creation
CONFIDENTIAL
MasterClock (MCLK)
Some MHz to 33 MHz
LCDTimingClock (TCLK)
5MHz~10MHz
SUBLCDTimingClock
(STCK) XIN clock
Clock
LowSpeedClock (LCLK)
Generator
100 kHz~200 kHz
PWMClock (PCLK)
XIN clock
MPEGClock (MPCLK)
15.36MHz or XIN
CameraClock (CAMCK)
Approx.16.128 MHz
RAM for mag/dif/sol
For error diffusion
LINE_Buffer (160 pixels x 36 x 1)
Buffer RAM for 1 line
For magnification function/
3D data sort function
RACK
LINE_Buffer (160 pixels x 48 x 4)
Buffer RAM for 1 line
RACK
Buffer RAM for 1 line
Buffer RAM for 1 line
Buffer RAM for 1 line
VideoSignalProcessor
WACK
Magnify
Magnification
circuit
WREQ
Diffusion
Error diffusion
72
circuit
Solidify
Buffer
3D circuit
18bitx4
72bit BS_DATA[71:0]
Buffer
BS circuit
18bitx4
MaskBit Memory
320x240
SEL
Pixcel
(2bit)
Magnify
Solidify
Magnification
3D circuit
circuit
Display Memory
Available for
MPEG4
Buffer section
BUF_
BUF_
DATA1
DATA0
Commonly used
for sub-LCD
VRAM
Conversion
External
PIO for
from YUV to RGB
clock
MPEG4ASIC
output
control
YUVIN0,2
UV determination
and latch circuit
Conversion from
8-bit to 16-bit
TEST
····· VRAM/HOST/HS/BS/
VDIF/VSPetc
····· TG/Pallet/LCD IF
/CDE/BS
····· SUB
····· SIO
····· PWM
·····External MPEG4_ASIC
·····External CAMERA_DSP
Registor
Available for
Address
Bus
magnification
Controller
Generator
function
Memory Interface
·18 bit x 4
·Vertical and horizontal
access
(No limitation for the
start address)
·Available for mask bit
ColorDepthExpand
RED
Pallet
BLUE
Pallet
R[5:0]
Palette
B[5:0]
I/F
6bit
320x240
Pixcel
6bit
(18bitx4
=72bit)
6bit
17bit
Available for sub-LCD
130,000 colors
Equivalent to LR38840
CPU_DataBus
I/F
17
8bit
DB[7:0]
Timing
4SCAN FRC
Control
TM200 OTHERS
6 - 14
SE_LD2/PORT5
FULL
SE_LD3/PORT6
Scan
PWM0/PORT3
PWMLCD/PORT4
PWM1/PORT8
Display size
320 x 240
Pixel
260,000
colors
RW
Command
function
(Trans-
mission)
Available for
260,000 colors
LCD
I/F
RDATA[5:0]
GDATA[5:0]
BDATA[5:0]
SE_DO/PORT0
SE_CK/PORT1
SE_LD1/PORT2
SE_DI/PORT7
DCLK
HSYNC
VSYNC
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