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IC702 VHITK11131C-1R (TK11131C): REGULATOR
Pin
Terminal
Input/
No.
name
Output
1
CONT
Input
Control
2
GND
-
Ground
3
NP
Input
Capacitor (Vref)
4
VOUT
Output Output
5
VIN
Input
Input
VIN
5
Over Heat &
Control
Over Current
Circuit
Protection
320K
Bandgap
Reference
500K
1
CONT
GND
IC704 (LR38863): DISPLAY CONTROLLER
Pin
Terminal
Input/
No.
name
Output
1
DUMMY4
-
2
VDDPLL
-
-
3
PLLGND
4
PLLDIV0
Input
5
PLLDIV1
Input
6
HSD0
Input/
Output
7
HSD1
Input/
Output
8
HSD2
Input/
Output
9
HSWRD
Input/
Output
10
HSEN
Input/
Output
11
HSCK
Input/
Output
-
12
DUMMY3
13
PWM1/PORT8
Output PWM output 1 General-purpose
14
PLLDIV2
Input
15
VDDCORE
-
16
GND
-
17
SUBWR_B
Input/
Output
CONFIDENTIAL
Description of terminal
VOUT
4
- +
3
2
NP
Description of terminal
Dummy 4
PLL Power supply 1.8 V (1.6 V~ 2.0 V)
PLL Ground
PLL multiply switching signal
PLL multiply switching signal
Data bus for high-speed serial transfer
Data bus for high-speed serial transfer
Data bus for high-speed serial transfer
Read/Write determination signal for
high-speed serial transfer
High-speed serial data effective
signal High is active
Standard clock for high-speed
serial transfer (5 to 33 MHz)
Dummy 3
PORT output (default) (Not used)
PLL multiply switching signal
CORE Power supply 1.8 V
(1.6 V~ 2.0 V)
Logic ground
Light signal for External display
Pin
Terminal
No.
name
18
GND
19
VDDCORE
20
PWM0/PORT3
21
SUBCS_B
22
CS_B
23
VDDIO
24
LCDINT
25
GTDIO_B
26
VDDIO
27
SUBDB1
28
BDATA[5] (B5)
29
BDATA[5] (B4)
30
BDATA[5] (B3)
31
GND
32
TESTI
33
BSHS_B
34
WR_B
35
SUBRS
36
MP4 RESET_B
37
HSD6
38
BDATA[2] (B2)
39
BDATA[2] (B1)
40
BDATA[2] (B0)
*
41
EXCS_B1
*
42
XOUT
43
VDDIO
44
GND
45
SCANEN
46
RD_B
47
RSP
48
GND
49
HSD3
50
DCLK
TM200 OTHERS
6 - 11
Input/
Description of terminal
Output
-
Logic ground
-
CORE Power supply 1.8 V
(1.6 V~ 2.0 V)
Output PWM output 0 General-purpose
PORT output (default)
Input/
Chip select signal for External display
Output
Input/
Device select signal (Display is
Output
active when CS_B is "Low")
-
IO Power supply 3.0 V (2.7 V~ 3.3 V)
Output External interrupt signal (Starting
varies when interruption occurs.)
Output MPEG4ASIC internal core power-
cut signal ("Low" is active.)
-
IO Power supply 3.0 V (2.7 V~ 3.3 V)
Input/
Data bus for External display
Output
Output Display panel B output signa
Output Display panel B output signa
Output Display panel B output signa
-
Logic ground
Input
Test terminal (Connected to GND
normally)
Input/
External Bit Stream horizontal
Output
synchronization signal ("Low" is active)
Input/
Host write strobe signal
Output
Input/
Data determination signal for
Output
External display
Output MPEG4ASIC reset control signal
("Low" is active)
Input/
Data bus for high-speed serial transfer
Output
Output Display panel B output signal
Output Display panel B output signal
Output Display panel B output signal
Input/
Chip select output 1 (internal
Output
decode output) (Not used)
Output Oscillation circuit output (Not used)
-
IO Power supply 3.0 V (2.7 V~ 3.3 V)
-
Logic ground
Input
Full scan effective signal "High" is
active (Connected to GND normally)
Input/
Host read strobe signal
Output
Input/
Register selection signal
Output
HOST_IF section :
RSP =Low...Display access
RSP = High...Control access
Hyper_Serial section :
RSP = Low...Control acces
RSP = High...Display access
-
Logic ground
Input/
Data bus for high-speed serial transfer
Output
Input/
Data sampling clock (display clock)
Output
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