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* Q502
uPD43256BGU-B12
S-RAM
262144 BIT
(512 X 512)
MEMORY
CELL ARRAY
f. Oo
ADDRESS
BUFFER
Address
input
Address
input
Address
input
Address
input
70
i70
70
|- [ono
input
output
1/0]
Data
input
output
Data
input
output
Address
input
Output
enable
inout
-63-
PCS 79 306
———
Vee
-——
GND
* Q551
27
28
& PEAK
SAA2003
SFC3
SU8-BAND
SER'AL
INTERFACE
STEREO SUB-BAND
FILTER PROCESSOR
FILTERED
MICROPACC
?
INTERFACE
DATA
InterFace,
[we ESET_J}
INTERFACE
& CONTROL
[_ STANDBY T
OETECTOR
Y
'EC 988
OUTPUT
filtered serial data input (from ADAS)
filtered data bit clock
filtered data word select
22.5792 MHz buffered clock output
22.5792 MHz XTAL oscillator output
22.5792 MHz XTAL oscillator input
24.576 MHz XTAL oscillator output
24.576 MHz XTAL oscillator input
24.576 MHz buffered clock output
L3 interface serial data
L3 interface bit clock
L3 interface mode control
LT compatible interface mode control
LT compatible interface mode control
test mode select
test mode select
unreliable data from drive processing
sub-band data direction
sub-band serial data
sub-band bit clock
sub-band word select
sub-band error flag from drive processing
VSS1
supply ground (logic)
VDD1
positive supply (logic)
IECOP
O
|TEC958 digital audio output
DAC control or general purpose output
DAC control or general purpose output
DAC control or general purpose output
master audio clock input from external source
master audio clock at 256 X sample frequency
positive supply (FS256 pin)
supply ground (FS256 pin)
PASC mode encode/decode
settings synchronisation for DAIO
sub-band 0 sample synchronisation
filtered serial data output (to ADAS)
* Q601
LTCNT1
LTCNTO
L3MODEM
L3CLKM
L3DATAM
VSS
LTCNTIC
LTCNTOC
L3MODEC
LICLKC
— OWONADUNbWHN
=
~o4
4 PWN
SAA2013
LTCNT1
LTCNTO
L3MODEM
L3CLKM
L3DATAM
~64—
ADAS
SFC3COMP
FDIR FRESET FSYNC FDAI
FDAO
FOCL
FOWS
PWROWN
CONTROL
ANO
TIO
SYNC
POR
LOWPWR
CLK24
ALLOCATION AND SCALE FACTOR
—
COMPUTATION
vOO
RESET
NODONE
Function
ADAS2 (SAA2012) interface mode control
ADAS2 (SAA2012) interface mode control
microcontroller interface mode
microcontroller interface clock
supply ground
SAA2002 SFC interface mode control
$AA2002 SFC interface mode control
codec interface mode
codec interface clock
codec interface data
(test output)
(test output)
positive supply
(test mode input) connect to VOD
(test mode input) connect to VDD
(test input) connect to VSS
(test input) connect to VSS
(test input) connect to VSS
No done state selection
resolution selection 0
resolution selection 1
active high reset input
positive supply
supply ground
24.576 MHz clock input
Low power playback select
Power On Reset
(test input) connect to VSS
power down input
word select filtered-I2S (F-12S) bus
bit clock F-12S bus
output data F-I2S bus
input data F-I2S bus
subband synchronisation on F-12S bus
reset signal from codec
F-125 bus direction
SFC3 (SAA2003) compatibility mode
system clock, 256 x sample frequency
positive supply
(not connected)
(not connected)
(not connected)
supply ground
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