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PCS 79 302
| MAIN
1 P503-1/4 (Page 37)
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FROM
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(Page 39)
=55i
K) IC BLOCK DIAGRAM AND TERMINAL FUNCTION OF IC'S
-QA01
TDA1315
DAIO
*SseL
12SOUTEN
FRAME &
BIPHASE
DEMOOULATOR
ERROR
NON
AUDIO DATA
||
OETECT.
a
Pa
3}
VOOA
-
positive supply voltage (analogue
part)
vO001/2
positive supply voltage (digital part)
VSSA
-
power supply return (analogue
ground)
vSS01/2
power supply return (digital ground)
IECINO
TTL-level
IEC input
HECINY
high-sensitivity IEC Input
{ECSEL
select IEC input 0 or 1
(0 = 1ECINO,
1 = 1ECIN1),
this Input has an internal pull-up resistor
t€COUT
digital audio output for optical and transformer link
IECOUTEN
digital audio output enable
(0 = enabled,
1 = disabled/tristate),
this input has an internal
pull-up
resistor
SO
serial audlo data (12S)
SCK
serial audio clock (I2S)
ws
word select (12S)
SOAUX
auxiliary serial data Input (I2S)
I2SSEL
select auxiliary Input or normal
input in transmit
mode
(0 = SDAUX,
1 = SO),
this Input has an internal pull-up resistor
l2SOUTEN
serial audlo output enable
(0 = enabled,
1 = disabled/tristate),
this input has an Internal
pull-up
resistor
audio mute
(0 = permanent
mute,
1 = mute
on receive
error),
this input has an internal
pull-up
resistor
select microprocessor/stand-alone moce
(0 = microprocessor, 1 = stand-alone),
this input has an internat
pull-up
resistor
SYSCLKO
system clock output (in receive mode)
SYSCLKI
system clock input (in transmit mode)
CLKSEL
select system clock (256 / 384 * f,)
(0 = 384 "fs, 1 = 256 * f,),
this input has an internal
pull-up
resistor
RCint
pin for integrating capacitor
RCfil
pin for PLL loop filter
Veet
js
pin for decoupling
of internal reference
voltage
STRCBE
strobe for control register (active high)
this input has an internal pull-down
resistor
LOATA
wP interface data line
LCLK
HP interface clock line
LMOOE
pP interlace mode line
LADOR
uP interface address
switch
(0 = 000001, 1 = 000010),
UDAVAIL
synchronization for user data
(0 = data available, 1 = no data)
UNLOCK
PLL out-ol-lock
(0 = not locked, 1 = jocked),
this output can drive a LED
INVALID
validity of audio sample
(0 = valid sample,
1 = invalid sample)
this pin has an internal
pull-down
resistor
CHMODE
usage of channel status block
(0 = professional use, 1 = consumer
use)
this output can drive a LEO
FS32
indicates sample frequency = 32 kHz (active low)
this output can drive a LED
FS44
indicates
sample frequency = 44.1
kHz (active low)
this output can drive a LED
FS48
indicates sample frequency = 48 kHz (active low)
this output can drive a LED
COPY
copyright
status
bit (0 = copyright
asserted,
1 = no copyright asserted)
this output can drive a LED
OEEM
pre-emphasis bit
(0 = no pre-emphasis, 1 = with pre-emphasis)
RESET
initialization after power-on, requires only an external capacitor to VOD
this is a Schmitt
trigger input with an internal
pull-down
resistor
PWROWN
enable
power down
(standby
mode)
(0 = normal
application,
1 = standby mode)
TESTA
enable factory test
(0 = normal application, 1 = test clock enaoled)
TESTB
enable factory test
(0 = normal
mode,
1 = scan
mode)
TESTC
enable factory test
(0 = normal
apptication,
1 = observation
outputs)
-56—-
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