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* Q201
TDA1381
WRITE3
voo voo vOO vOO voO voo v00 voo
Ttttrt
AMPLP
sAMPLN
ANP _O
VOLTAGE
ABIAS
REFERENCE
ANO
BIAS
VREF
CLK
WORTA
STANOBY
AB
TOA1381
YSET
CURRENT
CONTROL
VC_CNY
CSET
VSS
VSS
YSS
* Q391
TDA1309H
LOVAC
vouTe
DaACL
VSS OPA
VOD OPA
BAOL
ALA
AB
ALC
AD
RE
ALF
ALG
AH
Al
ALJ
& 3
ig
WOBNOWAWN
[awe [DESCRIPTION
7
standby mode control input
jaa
tape sector select input
opamp output
opamp
inverting input-
vi
positive supply voltage
vi
positive supply voltage
AB
13
B_J
sector B write pulse output
sector B write pulse output
Pre [trot connected)
_H
(not connected)
B
sector B write pulse output
B_G
sector B write pulse output
18
B_LF
sector B wrile pulse output
— = =
N
on
ny
+ Q501
vse
Ve_CRV
[ground
sd
set
31
Vss
ground
reference
vollage outpul
32
VREF
33 [ REIAS
Yoo
a
:
a
AC
5
Nn
nN
"
ROMUX __
~VREFP.
w uw
w
36
oS a
a
N
a|>
2 |'o
> m
VODDA-DA
VSSA-DA
VSSD-AD/DA
VODO0-AD/DA
OAPON
OADEM
SYSCLK
ADSDA
MODE1
MODE2
CLKEDGE
sector B write pulse output
B.C
(not connected)
a8
44
5
n.c.
23
47
48
@ >
a Le
un
NLR]
=-|O};o
ALJ
3 [Ar
AG
(not connected)
NOTE : Section A and section B are connected in reverse on this model.
fone [ee
pen «C=C enews
input
A/D
Bit clock = 32.f, or 64.f,
input
A/D
Word Select = f,
input
A/D D/A
Mode selection
input
A/D
Serial Data enable
output
A/D
Overload flag left and right channel
input
A/D
Power On mode (H = power on)
supply
A/O
Analog ground
supply voltage
supply
A/O
Analog
positive supply voltage
input
A/D
Negative reference voltage input (gnd)
decoupl
A/O
Decoupling
capacitor
decoupl
A/O
Positive reference voltage decoupl. cap.
output
A/D
Input amplifier output left
input
A/O
Input amplifier virtual ground left
Input
A/D
Input amplifier virtual ground right
output
A/D
Input amplifier output right
decoup!
A/O
Oecoupling capacitor
Input
A/D
D/A
Reference
current resistor
decoup!
O/A
Oecoupling capacitor
supply
A/D D/A
Opamps analog positive supply voltage
supply
A/O
D/A
Opamps
analog ground supply voltage
output
D/A
DA voltage output left
output
O/A
OA current output left
output
D/A
DA current output right
output
D/A
DA voltage output right
supply
D/A
Analog positive supply voltage
supply
D/A
Analog
ground
supply voliage
supply
A/D D/A
AD/DA digital ground supply voltage
supply
A/D D/A
AD/DA digital positive supply voltage
input
O/A
Power On mode (H = power on)
input
D/A
DA Digital de-emphasis
input
D/A
Bit clock = 32.f, or 64.1,
input
O/A
Word Select = {,
supply
A/D D/A
Digital filtzrs ground
supply voltage
supply
A/O D/A
Digital filters positive supply voltage
input
O/A
Serial data
input
A/O D/A
Analog loopthrough (High is loopthrough)
input
A/O D/A
Enable test mode (Low is normal mode)
input
A/D D/A
Enable test mode
(Low is normal
mode)
supply
A/O D/A
Digital 1/O ground supply voltage
mput
A/O D/A
System clock, SCK
= 256.1,
output
A/O
Serial Data
input
A/O D/A
Mode
selection
input
A/D
D/A
Mode
selection
input
A/O DJA
Bit clock rising/falling edge
-61-—
ee)
|
|
VO ImA
Word select for SB-I2S interface
SBCL
YO mA
Bit clock for SB-I2S intertace
VO IMA
Date line for SB-I2S intertace
mE
SBDIR
SBMCLK
[oima
| Direction line for SB-I2S interface
fo
Master clock for SB-I2S interface
~
L3MODE
Mode line for L3 interface
L3CLK
Bit Clock line for L3 interface
L3DATA
0 2mA
Serial data line for L3 interface
i
L3INT
voo1
vssi
L3REF
10
Jo1ma |
jp
jp
[Digital
ground
Jorma
|tsbus timing reference
i
[Reser nr ene
[i
[Pu DAP into power down mode
VT
[oma
|
Jorma |
[ota
|
Joima |
{
[oie
«vod
|
|
|
CLK24
x
G = ay
x
af
m1
ii
24.576 MHz clock input
i
chennel O end channel 7 azimuth monitor
f
6.144 MHz clock output
|
PRGSTAT
ERCOSTAT
TFE3 program stetus,
for test only
O ImA
ERCO status, for test only
[oama [ovat EnabisfosRAM
[oama [Adare SRam: RAS
ORAM
fp
[remer digs «von
SSS
CS
er
vss2
VO 4mA
Dete SRAM;
[voama_|owesrams
SSS
[vo sma [ete SRAM: Ons DRAW
iY
[rower oie gourd orRAM
|
[aasrensSRawiadsrees
ORAM
|
VOOR
Address SRAM;
Address ORAM
Address SRAM; Address DRAM
[Powerdigtal ground
Digital OF uN Fa
siviviyviy
wloa
40
vss3
SAA3323.
DRP
—————
Type
|
vo0o03
Power digital
+ VOD
Address SRAM; Address ORAM
Address SRAM; Address ORAM
UI
> N
Address SRAM: Address ORAM
Address SRAM; Port expander output 5
Al4/PinO1
A16/Pin03
Address SRAM; Pon expander output 1
4?
Address
SRAM:
Port expander
output 3
Address SRAM; Port expender output 4
Write enable for RAM
Address SRAM: Port expender output 2
Address SRAM; Address ORAM
Power digital
+ VOD
_
fl
< un un -
Power digital ground
Address SRAM;
CAS
for DRAM
Address SRAM;
PinO2/SPEEOB
[tcLock
|
VREFP
VREFN
PWM capstan contro! output for deck
Port expander
output
2 / PWM
capetan control output
fer deck
B
|
Serie! output to WRITE AMPLIFIER
3.072 MHz clock output for tape 1/0
Power digitel ground
Power digital
+ VDO
Analogue mpx'ed input from REAO
AMP
AOC
reference voltage P
'eference voltage N
<i<
ao
BBE
n
>|>
4
2
connection
rrr
2Il>
Ol2
al>
Z|2
ajm
a}>
slo
gio
2]. 3
Bias current for AOC
Anslogue ground
Analogue + VOO
Analogue
eye pattern output
Synchronization output for READ AMP
Power digital
+ VOD
_
~ rey
z
s
[cHtstz
i
é
7
[testy
|
1
" a
Power digital ground
Port expander input
!
Port expander output 1
SB-I12S error fleg ine
Where: | = input, la = analogue input, Id = input with pull-down resistance, Ih = hysteresis input,
VO = bidirectional, O = output, tO = tri-state output, P = power.
~62-
PCS 79 305
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