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* Q001
TC9192AF
MOTOR CONTROLLER
VOLTAGE
CONTROLLED
OSCILLATOR
142560
DIVIDER
iz
1720
i
17286
DIVIDER
DIVIDER
See
Se
a
a
a
EES
TS
ECE
ASST
=
Td
SPLED
NONITOR
are
172
*
TIMING DIVIDER
REVERSE
ROTATION
DIVIDER
(12
sits)
DETECTING CIRCUIT
S-BIT D/A
CONVERTER
SYNCHRONIZING
CrACUIT
REMARKS
GND
2
Fret
Reference
frequency
input
terminal
for phase
C-!OS
input
re
comparator.
3
Fe;
1/2560
dividing
output
terminal
of VCO
frequency,
C-NOS
outpuc
$18
internally comparison
signal is made.
Switching
terminal
of lock
range.
at LW="L"
normal
rahee.
at LW="'"',
double
range.
resistance
speec
Pulse
input
cerminal
for indicating
the
rotation
Built-in
amp.
8
Output
terminal
of APC
8-bit
D/A
converter
Built-in
bipola:
ssl
output.
transistor
Output
terminal
fo AFC 8-bit
D/A converter
Built-in
bipoler
BEE
output.
Vv
transistor
Output
terminal
for reference
voltage.
FUNCTION,
OPERATION
Power
supply
voltage
terminal
and
grounding
1
terminal.
Built-in
pull-uz
E
Built-in
bipola'
transistor
C-NOS
output
Built-in
pull-cus
resistance
Current
control
terminal
for controlling
VCO
C-NOS
output
frequency.
Current
control
output
terminal
for VCO
:
Nch open
drain
vc
Voltage
control
input
terminal
for VCO
DO
10
ad
°
Reverse
rotation
signal
for output
driver.
RUN/STOP
switching
terminal
of motor
at
RIS="L",
RUN.
act
RIS="H'"',
STOP
Lock
detecting
terminal.
When
the
rotation
frequency
is within
lock
range,
"H'
level,
and
in other
cases,
"L"
level.
ay N
RIS
ay w
a
aa
Ww
a t
i=]
Terminal
attached
with
capacitor
for adjuscing
frequency.
Internal
control
signal
is made.
14
RL
rw N
~ (ce)
Output
terminal
of phase
comparator
C-10S
output
— ve)
Input
terminal
of internal
test.
C=MOS
input
Generally
ground.
Test
-
-59-
PCS 79 304
- Q101
TDA1380
READ3
INX25A
INXOA
INOVA
INIA
RDSYNC
IN23A
IN34A
IN4A
INS6A
DSENADJ1
DSENADJ2
ING7A
DSENADJ3
ates z
by VREFSENA
INTA
VREFSENB
INX25B
INXOB
INDIE
TDA1380
INDE
OUTEOL
INEOL
IN238
OUTLA
OUTLB
IN34B
OUTRA
IN4B
OUTRB
INEOR
INS6B
OUTOER
IN67B
INMFR
MFR2A
ree
MFRIAB
MFR2B
vo0
o
VSS
©
VCCMOQ VEFMc)
DESCRIPTION
SYMBOL
| OSENADI1 | 1 | Adjust pin for DCC sense current 1 (A,B)
Posenagsa | 2 | Advt in for OCC sees curent
21S)
Posenagss [3 | Aduet pin for OCC sense curent
3A)
Pvacrsewa [a | Rearence voltage ouput BCC renee A)
| §_|
| 6 |
OCC sense current output 1 (B)
OCC sense current output 2 (8)
Posense |e | occ sense curentoupue 3
SOSSCSCSCSC~*S
Posensa | 9 | Oct sense curent oun 3
SSSCSCS*SY
Posenza [10 | Occ sense curentouput
2A)
Posenta [11 | 000 sensecurentouput
iQ)
Pinos [12 _[ Asiary enenoeinpu renernel @mee@)
fino [13 etennat 9 put
pera [1a [etemnet Vint
Channel AUX / 2/5
input (8)
IN238
Channel
2 / 3 input (B)
17
Channel! 3 / 4 input (B)
Channel
4 input (8)
Channel
5 / 6 input (B)
Channel
6 / 7 input (8)
IN67B
IN7B
Channel
7 input (B)
Channel
7 input (A)
Channel 6 / 7 input (A)
Channel
5 / 6 input (A)
IN4A
IN34A
Channel 4 input (A)
Channel
3 / 4 input (A)
l
27
Channel 2 / 3 input (A)
Channel AUX / 2/5
input (A)
Channel
1 input (A)
INX25A
INTA
Channel 0 / 1 input (A)
INXOA
v10
MFR2B
MFR1AB
MFR2A
INMFR
OUTRA
OUTRB
Right channel ACC output (A)
Right channel ACC output (B)
37
|
MFL2A
Ground
for feedback
amplifiers
Left channel! ACC output (A)
AOC reference voltage output
o
Tape side A or B selection input
ROSYNC
ROCLK
so
S4
Read
sync pulse input
Read clock pulse input
Select OCC mode input
Wi
S
General ground
8
General positive supply
oO wn
> <j<
by
ro)
Chip select input
G
VBIAS
RDMUX
OUTX
MUXINX
AGC time constant
Auxiliary channel multiplexer input
—~60-—
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