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Schematic Diagrams
Ivy Bridge Processor 2/7
PU/PD for JTAG signals
VTT_CPU
3.3VS
Sheet 3 of 43
Ivy Bridge
Processor 2/7
17,23
B - 4 Ivy Bridge Processor 2/7
Ivy/Sandy Bridge Processor 2/7
R416
51_04
XDP_TMS
R108
51_04
XDP_TDI_R
XDP_PREQ#
R109
*51_04
XDP_TDO_R
R415
51_04
XDP_TCLK
R414
51_04
R95
51_04
XDP_TRST#
H_SNB_IVB#
18
H_SNB_IVB#
R407
1K_04
XDP_DBR_R
H_CATERR#
R411
*10mil_04
H_PECI_R
18,27
H_PECI
R405
56_1%_04
H_PROCHOT#_D
36
H_PROCHOT#
If PROCHOT# is not used, then it must
be terminated with a 68-£[ +-5%
pull-up resistor to 1.05VS_VTT .
R417
*10mil_04
H_THRMTRIP#_R
18
H_THRMTRIP#
R419
*10mil_04
PM_SYNC_R
15
H_PM_SYNC
H_CPUPWRGD_R
R418
*10mil_04
18
H_CPUPWRGD
PMSYS_PWRGD_BUF
VDDPWRGOOD_R
R60
130_1%_04
Buffered reset to CPU
VTT_CPU
BUF_CPU_RST#
R105
75_1%_04
R104
43_1%_04
6
3.3VS
D
Q36A
R530
10K_04
2
G
L2N7002DW1T1G
S
3
1
D
5
G
Q36B
S
L2N7002DW1T1G
4
R112
*1.5K_1%_04
PLT_RST#
27
H_PROCHOT_EC
R531
C96
R106
100K_04
*68p_50V_NPO_04
*750_1%_04
10/1
CAD Note: Capacitor
need to be placed
close to buffer output pin
( CLK,MISC,JTAG )
U34B
A28
BCLK
C26
A27
PROC_SELECT#
BCLK#
AN34
SKTOCC#
A16
DPLL_REF_CLK
A15
DPLL_REF_CLK#
AL33
CATERR#
AN33
R8
CPUDRAMRST#
PECI
SM_DRAMRST#
AL32
AK1
SM_RCOMP_0
PROCHOT#
SM_RCOMP[0]
A5
SM_RCOMP_1
SM_RCOMP[1]
A4
SM_RCOMP_2
SM_RCOMP[2]
AN32
THERMTRIP#
AP29
XDP_PRDY #
PRDY#
AP27
XDP_PREQ#
PREQ#
AR26
XDP_TCLK
TCK
AR27
XDP_TMS
TMS
AM34
AP30
XDP_TRST#
PM_SY NC
TRST#
AR28
XDP_TDI_R
TDI
AP26
XDP_TDO_R
TDO
AP33
UNCOREPWRGOOD
AL35
XDP_DBR_R
DBR#
V8
SM_DRAMPWROK
AT28
XDP_BPM0_R
BPM#[0]
AR29
XDP_BPM1_R
BPM#[1]
AR30
XDP_BPM2_R
AR33
BPM#[2]
AT30
XDP_BPM3_R
RESET#
BPM#[3]
AP32
XDP_BPM4_R
BPM#[4]
AR31
XDP_BPM5_R
BPM#[5]
AT31
XDP_BPM6_R
BPM#[6]
AR32
XDP_BPM7_R
BPM#[7]
PZ98827-364B-01F
H_PROCHOT#
Q14
G
MTN7002ZHS3
C515
47p_50V_NPO_04
R91
100K_04
R90
*0_04
2,5,18,19,20,34,35,36
2,6,11,13,14,15,17,18,19,20,22,23,26,27,28,31,33,34,35
9,10,11,12,13,14,15,16,17,18,19,20,23,24,25,27,28,29,30,31,36
Processor Pullups/Pull downs
H_PROCHOT#
R410
62_04
H_CPUPWRGD_R
R412
10K_04
C585
*0.1u_10V_X7R_04
TRACE WIDTH 10MIL, LENGTH <500MILS
DDR3 Compensation Signals
CLK_EXP_P 14
CLK_EXP_N 14
SM_RCOMP_0
R413
140_1%_04
CLK_DP_P 14
SM_RCOMP_1
R382
25.5_1%_04
CLK_DP_N 14
SM_RCOMP_2
R381
200_1%_04
S3 circuit:- DRAM PWRGOOD logic
3.3V
1.5V_CPU
R73
R57
*200_1%_04
10K_04
D20
1
A
15
PM_DRAM_PWRGD
3
C
2
A
15,33
1.8VS_PWRGD
*BAT54AS3
R58
*39_04
R59
*10mil_04
Q10
G
31,33,34
SUSB
*MTN7002ZHS3
S3 circuit:- DRAM_RST# to memory
should be high during S3
1.5V
R47
*0_04
R45
1K_04
Q8
MTN7002ZHS3
CPUDRAMRST#
S
D
R48
1K_04
DDR3_DRAMRST# 9,10
R46
DRAMRST_CNTRL 9,10,14
C22
0.047u_10V_X7R_04
ÂÅ ¤Ñ ¹q ¸£ CLEVO CO.
VTT_CPU
Title
[03]PROCESSOR 2/7
6,31
1.5V_CPU
6,9,10,20,28,31,33
1.5V
3.3V
Size
Document Number
3.3VS
A3
Date:
Friday , Nov ember 18, 2011
Sheet
VTT_CPU
PMSY S_PWRGD_BUF
Rev
3.0
3
of
43
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