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3.3 Header Translation
The µ PD98410 translates headers in accordance with the header translation table (HTT) created in the external
SRAM. Headers are translated when a cell is input in the single-cast mode, and when a cell is input or output in the
multi-cast mode. The HTT is created by an external microprocessor when connection is made.
The format of the HTT and header translation procedure are explained below.
3.3.1 HTT (Header Translation Table) memory map
The HTT (Header Translation Table) is located in the HTT & control memory as Area-A and Area-B. The following
three types of memories can be connected to the µ PD98410 as the HTT & control memory.
for 1 M-bit (×18) SRAM × 2
AD [19:0]
31
3FFFFh
Control Memory
µ
(used by PD98410)
20000h
1FFFFh
1,024-channel
10000h
64-byte
0FFFFh
16,384-channel
4-byte
00000h
Remarks 1. The addresses shown in this figure are those accessed by the microprocessor.
2. The µ PD98410 divides address AD[19:0] from the microprocessor by four and access the HTT &
control memory in word units where one word consists of 4 bytes. Therefore, HTA[17:0] output an
address that is divided by four.
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CHAPTER 3 FUNCTIONAL OUTLINE
Figure 3-17. HTT & Control Memory Map
for 1 M-bit (×9) SRAM × 4
AD [19:0]
0
31
7FFFFh
Control Memory
µ
(used by PD98410)
40000h
3FFFFh
2,048-channel
20000h
64-byte
1FFFFh
32,768-channel
4-byte
00000h
for 4 M-bit (×18) SRAM × 2
AD [19:0]
0
31
FFFFFh
Control Memory
µ
(used by PD98410)
80000h
7FFFFh
4,096-channel
40000h
64-byte
3FFFFh
65,536-channel
4-byte
00000h
Area-B: Multicast bitmap & Output VPI, VCI
Area-A: Header translation table for channel
0
Area-B
Area-A
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