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3.11 Microprocessor Interface
The microprocessor can access the HTT & control memory and cell buffer memory via the µ PD98410, in addition
to the internal I/O registers of the µ PD98410.
• I/O registers
• HTT & control memory : Initial setting, connection setting to HTT, self-diagnosis
• Cell buffer memory
The µ PD98410 supports two interfaces for connecting a microprocessor: 32-bit multiplexed synchronous bus and
16-bit separated asynchronous bus. These buses are general-purpose bus interfaces that require fewer external
circuitry than ordinary I/O buses (PCI Bus, S Bus, A Bus, AP Bus, and 86 Bus).
The interface with the microprocessor is determined as follows, depending on the status of the HSEL input pin at
hardware reset.
32-bit Multiplexed Synchronous Bus
HCLK (Processor bus clock)
R/W_B (Read/Write mode)
UWE_B (Upper word enable)
AD [31:16] (Address/Data bus)
AD [15:0] (Address/Data bus)
RDY_B (Bus ready)
CHAPTER 3 FUNCTIONAL OUTLINE
: Initial setting, command issuance, status check, etc.
: Self-diagnosis
Table 3-13. Microprocessor Interface Pin
HSEL = Low
IOCS_B (I/O chip select)
MCS_B (Memory chip select)
INT (Interrupt request)
HSEL = High
16-bit Separated Asynchronous Bus
Pull up or pull down
WR_B (Write strobe)
RD_B (Read strobe)
A[15] (Pull up or pull down)
A[14:0] (Address bus)
D[15:0] (Data bus)
RDY (Bus ready)
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