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DP-7010
CIRCUIT DESCRIPTION
Function
MUI
1
PLL system mute input pin.
DMUT
1 | TBC system mute input pin (Mute at "H").
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INV
1 | Input data inversion (both Lch and Reh) (Inversion at "'H"').
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NC
- | Unused.
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WES
| | Write clock pulse synchronous with input data.
48
WwoOCK
|
Input word clock pulse.
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DIL
Leh input data.
50
DIR
Rch input data.
$1
Iw18
Data bit length selection (16-bit/18-bit = "'L"'/'H"').
52
WOCO
Digital fitter MEN signal.
53
Voo
Power supply {+5V).
MOT
Digital filter MOT signal.
Digital filter selection.
Read clock pulse synchronous with output data.
S192 clock pulse.
FS192 clock pulse inversion.
|
|
t
ie)
!
ie)
© | Digital filter A1/A2 input signal.
|
|
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ie)
FS1921
GND.
DP-7010
CIRCUIT DESCRIPTION
11-4. Functions
¢ TBC function
The write data clock pulse (WFS) and the read data
clock pulse (RFS) are independent in operation from
each other. Thus, the jitter margin ranges
+1
clock
pulse widths.
0
1000
2000
3000
4000
For 2MSB detection, the level (2's complement) of
the 2MLSB
detection value at playback is output for
both Leh and Rch.
Figure 11-1 shows the I/O waveforms in use of each
digital filter.
Signal : 1 kHz, o dB (At playback)
5000
6000
7000
ns
se
OT)
|
fy
Chan.
5 (DIR)
Time
: lps
Trig
: Chan. 3
Levet
: 4 (AUTO)
Zoom : x 2
Fig. 11-1 D.P.A.C timing chart
¢ PLL function
Since the phase comparator is of a well-known sys-
tem, its description ts not made here.
For the counter setting of the divider, the type of the
input clock pulse, LPF and VCXO circuit configuration,
etc., refer to "11-2 Block diagram" and "11-3 Pin func-
tions".
* Digital filter mode setting
Only two modes are available, 16-bit and 18-bit modes.
This unit is set at the 18-bit mode.
The mode change is performed at the time of muting.
The status right before the cancel of muting is held.
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