Advertisement
DP-7010
CIRCUIT DESCRIPTION
+» Data and DAC control signa! output (DOL, DOR,
BCKO, WCKO, DG, COB, OW18,0W20}
1) Output data format
1) MSB first
2) 2's complement/COB (Complemented Offset Binary)
selection (COB)
-
2's complement format (COB="H")
item
pela
COB format (COB="L")
2) Output data number-of-bits selection
(OW18, OW20)
As to the number of bits for the output data, any of 16,
18 and 20-bit can be selected.
16-bit output (OW18="H",
OW20="H")
18-bit output (OW18="L", OW20="H")
20-bit output (OW18="H", OW20="L")
However, this unit is set at the 18-bit output mode.
3) Output timing
The output timing of the audio output section is deter-
mined according to each internal system clock pulse
frequency.
Internal system
192s
clock pulse frequency
Bit clock pulse period —_ |
Tsys
Data word length
24*Tsys
Tsys : internal clock pulse period (Refer to Table*10-1.}
Th, Tw : serial output timing (Refer to Figure 10-6.)
Table 10-2 Output timing
H
Word Output Period
Tw
n bits
1
1
20—n bits —
t
t
1
CER
EE Eee Ee eee ee
ea
i
DOR
|
'
1
n
1
!
'
1
i]
BCKO
{
TP
ie]
es
esi
;
—™
Tb Me
a
Twi
3/4Tw
wero
i
t
(
t
'
rot
Fe
tT
|
Note : n means the number of output word bits.
Fig. 10-6 Output timing
+ System reset (RST)
When the reset input is made in the jitter-free mode,
the internal operation timing is reset in synchronization
with the leading edge of input LRCI. Making use of this,
the output timing in the jitter-free mode can be aligned
with input LRCI.
In the compulsory sync mode, no system reset is
needed. Even in the jitter-free mode, the output timing
does not need to be aligned with input LRCI and no
system reset is necessary.
For system reset at power ON, externally connect a
capacity of around 100pF to pin RST. (Figure 10-7)
SM5813AP
Fig. 10-7 Circuit example of system reset at power ON
40
DP-7010
CIRCUIT DESCRIPTION
10-9. Timing chart
® Serial input timing (DIN, BCKI, LRC?)
|
MsB
Loh data
LsB
MSB
Rich data
isa!
'Mora than Ocycle
!
16 cyctes
'
4!
More tan 0 cycle
16 cycles
Note : BCKI should have 18 cycies or more for one word,
Fig. 10-8 Serial input timing
© Serial output timing (DOL, DOR, BCKO, WCKO, DG)
Fig. 10-9 Serial output timing
41
Advertisement
