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DP-7010
38
CIRCUIT DESCRIPTION
10-8. Function
* 8x over-sampling (interpolation) filter function
This function works to output the over-sampling data
of sampling rate 8fs. In this case, sampling noises be-
tween 0.5465fs (24. 1kHz) and 7.4535fs (328.69kHz) are
2x
interpolator
153rd
removed.
(1st FIR)
The interpolation operation block configuration of this
LSI is of a cascade connection of three 2x interpolation
filters (FIR).
+ System clock (XTI, XTO, CKO, CKSL, CKDV)
ax
The system clock pulse can be selected from 192fs,
wae
256fs, 384fs and 512fs. More, operationis feasible even
Wastin!
by an external
clock (input to pin XT!) or a crystal
oscillator (inserted between pins XT/ and XTO). In this
unit, a clock pulse of 8.4672 MHz is input to pin XTI.
From pin CKO, the system clock pulse is output. (See
Figure 10-3.)
(3rd FIR)
OUTPUT
Fig. 10-2 Configuration of basic operation section
pK
4
CKSL
ee Se)
XTI input clock
Fxi
{
Clock pulse
input method
Internal system
clock pulse period
External clock {input to pin XTi) or internal clock
{a crystal oscillator inserted between pin XTI and XTO).
XI stands for the XTI input clock pulse period.
Table 10-1 System clock frequency selection and internal system clock
x a
LJ
eee
oe
ee ee
ee
ed
192/256
TIMING
Division Ratio Selection
COUNTER
RESET
Each Part Timing
Fig. 10-3 Clock generation circuit
DP-7010
CIRCUIT DESCRIPTION
+ Audio data input (DIN, BCKi, LRCI)
The input data is handled as being of 2's comple-
ment, MSB first. Each bit of the serial data input to pin
DIN is read in to register SIPO (serial/parallel conversion
register) a the leading edge of bit clock pulse BCKI, in
which it is in turn converted into a parallel data. The
output of SIPO is transferred to each of the Lch and Rch
input registers at the trailing/leading edge of clock pulse
LRCI.
In addition, the operation section and the output
section are independent in signal timing from the input
section and are therefore unsusceptible to the jitter of
the input section. (Jitter-free mote: For details, refer to
the description occurring later.)
¥
Fig. 10-4 Configuration of audio data input section
FSCK
oe
"
a
hn
ae
t
U
U
tryed
Timing of Take-in to Input SIPO
t
Input Register 1
(Aa—1) Taken
Clock |
Pulse / og
Input Register 2
(Ln-11 Take-in
Input Register 1
{Ln) Teke-in
(Ra) Take-in
oral
po ee
ell
(
Input Register 2
(Rin—1) Take-in
(Ln) Takein
Input Register 4
L
input Register 2
16bits right before LRC! edge is taken in as data.
Fig. 10-5 Audio data input timing example
« Selection between jitter-free mode and compul-
sory sync mode (SYN, FSCO)
The signal timing (internal timing) applied to internal
operation or output, that is produced from the system
clock pulse (input to pin XTI), is independent from that
of the data input section (BCK!, LRCI).
For this internal timing, the method of countering the
jitter of clock pulse input LRCI is available in two types,
"jitter-free mode" and "compulsory sync mode". Se-
lection between these both is feasible by setting SYN.
1) Jitter-free mode (SYN="H")
As long as the phase difference between clock pulse
LRCI and the internal timing is within +3/8 to -3/8 of the
input sampling period (1/fs), the internal timing is not
adjusted. Accordingly, even with a jitter component in
clock pulse LRCI, the internal timing is not affected so
that it is free from faulty operation or jitter transmission
to output.
When the phase difference is without the above
range, the internal timing is put in phase synchronously
with the start side of clock pulse LRCI. More, this
treatment is also performed when the reset input is
given.
Soe
2) Compulsory syne mode (SYN="L")
When this mode is engaged, the internal timing is
always reset at a pulse edge of the start side of input
LRCI. In this case, when a pulse period shorter than the
specified system clock pulse period exists due to the
jitter of input LRCI, a faulty operation may result.
Conversely, when a pulse period longer exists, the
operation is properly made but no equal output timing is
obtained.
3) Clock pulse FSCO (output)
This is a clock pulse with a period of fs obtained from
the dividing process of clock pulse XTI.
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