Processor 3/12 - Clevo NL40MU1 Service Manual

Processor 3/12

5
[15] M_B_DQ_0_7
D [15] M_B_DQ_0_6
[15] M_B_DQ_0_5
[15] M_B_DQ_0_4
[15] M_B_DQ_0_3
[15] M_B_DQ_0_2
[15] M_B_DQ_0_1
[15] M_B_DQ_0_0
[15] M_B_DQ_1_7
[15] M_B_DQ_1_6
[15] M_B_DQ_1_5
[15] M_B_DQ_1_4
[15] M_B_DQ_1_3
[15] M_B_DQ_1_2
[15] M_B_DQ_1_1
[15] M_B_DQ_1_0
[15] M_B_DQ_2_7
[15] M_B_DQ_2_6
[15] M_B_DQ_2_5
[15] M_B_DQ_2_4
[15] M_B_DQ_2_3
[15] M_B_DQ_2_2
[15] M_B_DQ_2_1
[15] M_B_DQ_2_0
[15] M_B_DQ_3_7
[15] M_B_DQ_3_6
DATA
[15] M_B_DQ_3_5
[15] M_B_DQ_3_4
[15] M_B_DQ_3_3
SINGLE=50ohm
[15] M_B_DQ_3_2
C
[15] M_B_DQ_3_1
[15] M_B_DQ_3_0
[15] M_B_DQ_4_7
[15] M_B_DQ_4_6
[15] M_B_DQ_4_5
[15] M_B_DQ_4_4
[15] M_B_DQ_4_3
[15] M_B_DQ_4_2
[15] M_B_DQ_4_1
[15] M_B_DQ_4_0
[15] M_B_DQ_5_7
[15] M_B_DQ_5_6
[15] M_B_DQ_5_5
[15] M_B_DQ_5_4
[15] M_B_DQ_5_3
[15] M_B_DQ_5_2
[15] M_B_DQ_5_1
[15] M_B_DQ_5_0
[15] M_B_DQ_6_7
[15] M_B_DQ_6_6
[15] M_B_DQ_6_5
[15] M_B_DQ_6_4
[15] M_B_DQ_6_3
[15] M_B_DQ_6_2
[15] M_B_DQ_6_1
[15] M_B_DQ_6_0
[15] M_B_DQ_7_7
[15] M_B_DQ_7_6
[15] M_B_DQ_7_5
B
[15] M_B_DQ_7_4
[15] M_B_DQ_7_3
[15] M_B_DQ_7_2
[15] M_B_DQ_7_1
[15] M_B_DQ_7_0
A
5
4 3
U21C
DDR4/LP4/LP5/LP5 CMD Flip
LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
AL53
DDR4_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7 DDR1_CLK_P1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P
AL52
DDR4_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6 DDR1_CLK_N1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK
AL50
DDR4_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P
AL49
DDR4_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4 NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK
AP53
DDR4_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3 NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P
AP52
DDR4_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2 NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK
AP50
DDR4_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1 DDR1_CLK_P0/DDR4_CLK_P/DDR4_CLKP/DDR4_CLK_P
AP49
DDR4_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0 DDR1_CLK_N0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK
AF53
DDR4_DQ1_7/DDR1_DQ1_7/DDR0_DQ5_7
DDR4/LP4/LP5/LP5 CMD Flip
AF52
DDR4_DQ1_6/DDR1_DQ1_6/DDR0_DQ5_6 NC/DDR7_CKE0/DDR7_WCK_P/DDR7_WCK_P
AF50
DDR4_DQ1_5/DDR1_DQ1_5/DDR0_DQ5_5 NC/DDR7_CKE1/DDR7_WCK_N/DDR7_WCK
AF49
DDR4_DQ1_4/DDR1_DQ1_4/DDR0_DQ5_4 NC/DDR6_CKE0/DDR6_WCK_P/DDR6_WCK_P
AH53
DDR4_DQ1_3/DDR1_DQ1_3/DDR0_DQ5_3 NC/DDR6_CKE1/DDR6_WCK_N/DDR6_WCK
AH52
DDR4_DQ1_2/DDR1_DQ1_2/DDR0_DQ5_2 NC/DDR5_CKE0/DDR5_WCK_P/DDR5_WCK_P
AH50
DDR4_DQ1_1/DDR1_DQ1_1/DDR0_DQ5_1 NC/DDR5_CKE1/DDR5_WCK_N/DDR5_WCK
AH49
DDR4_DQ1_0/DDR1_DQ1_0/DDR0_DQ5_0 NC/DDR4_CKE0/DDR4_WCK_P/DDR4_WCK_P
AR41
DDR5_DQ0_7/DDR1_DQ2_7/DDR1_DQ4_7 NC/DDR4_CKE1/DDR4_WCK_N/DDR4_WCK
AV42
DDR5_DQ0_6/DDR1_DQ2_6/DDR1_DQ4_6
DDR4/LP4/LP5/LP5 CMD Flip
AR42
DDR5_DQ0_5/DDR1_DQ2_5/DDR1_DQ4_5 DDR1_CKE1/DDR6_CA4/DDR6_CA5/DDR6_CA1
AV41
DDR5_DQ0_4/DDR1_DQ2_4/DDR1_DQ4_4 DDR1_CKE0/DDR6_CA5/DDR6_CA6/DDR6_CA0
AR45
DDR5_DQ0_3/DDR1_DQ2_3/DDR1_DQ4_3 DDR4/LP4/LP5/LP5 CMD Flip
AV45
DDR5_DQ0_2/DDR1_DQ2_2/DDR1_DQ4_2 DDR1_CS1/DDR5_CA1/DDR4_CA1/DDR4_CA5
AR47
DDR5_DQ0_1/DDR1_DQ2_1/DDR1_DQ4_1 DDR1_CS0/NC/DDR4_CS1/DDR4_CA4
AV47
DDR5_DQ0_0/DDR1_DQ2_0/DDR1_DQ4_0 DDR4/LP4/LP5/LP5 CMD Flip
AJ41
DDR5_DQ1_7/DDR1_DQ3_7/DDR1_DQ5_7 NC/DDR7_CA5/DDR7_CA6/DDR7_CA0
AJ42
DDR5_DQ1_6/DDR1_DQ3_6/DDR1_DQ5_6 NC/DDR7_CA4/DDR7_CA5/DDR7_CA1
AL41
DDR5_DQ1_5/DDR1_DQ3_5/DDR1_DQ5_5 NC/DDR7_CA3/DDR7_CA4/DDR7_CS1
AL42
DDR5_DQ1_4/DDR1_DQ3_4/DDR1_DQ5_4 NC/DDR7_CA2/DDR7_CA3/DDR7_CS0
AJ45
DDR5_DQ1_3/DDR1_DQ3_3/DDR1_DQ5_3 NC/DDR6_CS0/DDR6_CA2/DDR6_CA2
AJ47
DDR5_DQ1_2/DDR1_DQ3_2/DDR1_DQ5_2 NC/DDR4_CA1/DDR4_CA1/DDR4_CA5
AL45
DDR5_DQ1_1/DDR1_DQ3_1/DDR1_DQ5_1 NC/DDR4_CA0/DDR4_CA0/DDR4_CA6
AL47
DDR5_DQ1_0/DDR1_DQ3_0/DDR1_DQ5_0 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
A43
DDR6_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7 DDR7_DQSP_1/DDR1_DQSP_7/DDR1_DQSP_7
B43
DDR6_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6 DDR7_DQSN_1/DDR1_DQSN_7/DDR1_DQSN_7
D43
DDR6_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5 DDR7_DQSP_0/DDR1_DQSP_6/DDR1_DQSP_6
E44
DDR6_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4 DDR7_DQSN_0/DDR1_DQSN_6/DDR1_DQSN_6
A46
DDR6_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3 DDR6_DQSP_1/DDR1_DQSP_5/DDR0_DQSP_7
B46
DDR6_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2 DDR6_DQSN_1/DDR1_DQSN_5/DDR0_DQSN_7
D46
DDR6_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1 DDR6_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6
E47
DDR6_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0 DDR6_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6
E38
DDR6_DQ1_7/DDR1_DQ5_7/DDR0_DQ7_7 DDR5_DQSP_1/DDR1_DQSP_3/DDR1_DQSP_5
D38
DDR6_DQ1_6/DDR1_DQ5_6/DDR0_DQ7_6 DDR5_DQSN_1/DDR1_DQSN_3/DDR1_DQSN_5
B38
DDR6_DQ1_5/DDR1_DQ5_5/DDR0_DQ7_5 DDR5_DQSP_0/DDR1_DQSP_2/DDR1_DQSP_4
A38
DDR6_DQ1_4/DDR1_DQ5_4/DDR0_DQ7_4 DDR5_DQSN_0/DDR1_DQSN_2/DDR1_DQSN_4
E41
DDR6_DQ1_3/DDR1_DQ5_3/DDR0_DQ7_3 DDR4_DQSP_1/DDR1_DQSP_1/DDR0_DQSP_5
D40
DDR6_DQ1_2/DDR1_DQ5_2/DDR0_DQ7_2 DDR4_DQSN_1/DDR1_DQSN_1/DDR0_DQSN_5
B40
DDR6_DQ1_1/DDR1_DQ5_1/DDR0_DQ7_1 DDR4_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4
A40
DDR6_DQ1_0/DDR1_DQ5_0/DDR0_DQ7_0 DDR4_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4
G42
DDR7_DQ0_7/DDR1_DQ6_7/DDR1_DQ6_7
DDR4/LP4/LP5/LP5 CMD Flip
G41
DDR7_DQ0_6/DDR1_DQ6_6/DDR1_DQ6_6 DDR1_ODT1/DDR5_CA0/DDR5_CA0/DDR5_CA6
J41
DDR7_DQ0_5/DDR1_DQ6_5/DDR1_DQ6_5 DDR1_ODT0/DDR5_CS0/DDR5_CA2/DDR5_CA2
J42
DDR7_DQ0_4/DDR1_DQ6_4/DDR1_DQ6_4 DDR4/LP4/LP5/LP5 CMD Flip
G45
DDR7_DQ0_3/DDR1_DQ6_3/DDR1_DQ6_3 DDR1_MA16/DDR5_CA4/DDR5_CA5/DDR5_CA1
J45
DDR7_DQ0_2/DDR1_DQ6_2/DDR1_DQ6_2 DDR1_MA15/DDR5_CA3/DDR5_CA4/DDR5_CS1
G47
DDR7_DQ0_1/DDR1_DQ6_1/DDR1_DQ6_1 DDR1_MA14/DDR5_CA2/DDR5_CA3/DDR5_CS0
J47
DDR7_DQ0_0/DDR1_DQ6_0/DDR1_DQ6_0 DDR1_MA13/DDR5_CS1/DDR5_CS0/DDR5_CA3
G38
DDR7_DQ1_7/DDR1_DQ7_7/DDR1_DQ7_7 DDR1_MA12/DDR6_CA1/DDR6_CA1/DDR6_CA5
G36
DDR7_DQ1_6/DDR1_DQ7_6/DDR1_DQ7_6 DDR1_MA11/NC/DDR6_CS1/DDR6_CA4
H36
DDR7_DQ1_5/DDR1_DQ7_5/DDR1_DQ7_5 DDR1_MA10/DDR7_CA1/DDR7_CA1/DDR7_CA5
H38
DDR7_DQ1_4/DDR1_DQ7_4/DDR1_DQ7_4 DDR1_MA9/DDR6_CA0/DDR6_CA0/DDR6_CA6
N36
DDR7_DQ1_3/DDR1_DQ7_3/DDR1_DQ7_3 DDR1_MA8/DDR4_CA2/DDR4_CA3/DDR4_CS0
L36
DDR7_DQ1_2/DDR1_DQ7_2/DDR1_DQ7_2 DDR1_MA7/DDR4_CA4/DDR4_CA5/DDR4_CA1
L38
DDR7_DQ1_1/DDR1_DQ7_1/DDR1_DQ7_1 DDR1_MA6/DDR4_CA3/DDR4_CA4/DDR4_CS1
N38
DDR7_DQ1_0/DDR1_DQ7_0/DDR1_DQ7_0 DDR1_MA5/DDR4_CA5/DDR4_CA6/DDR4_CA0
DDR1_MA4/DDR4_CS0/DDR4_CA2/DDR4_CA2
DDR1_MA3/DDR4_CS1/DDR4_CS0/DDR4_CA3
DDR1_MA2/DDR7_CS0/DDR7_CA2/DDR7_CA2
DDR1_MA1/NC/DDR4_CS1/DDR4_CA4
DDR1_MA0/NC/DDR7_CS1/DDR7_CA4
DDR4/LP4/LP5/LP5 CMD Flip
DDR1_BG1/DDR6_CA2/DDR6_CA3/DDR6_CS0
DDR1_BG0/DDR6_CA3/DDR6_CA4/DDR6_CS1
DDR4/LP4/LP5/LP5 CMD Flip
DDR1_BA1/DDR5_CA5/DDR5_CA6/DDR5_CA0
DDR1_BA0/DDR7_CA0/DDR7_CA0/DDR7_CA6
DDR1_ACT#/DDR6_CS1/DDR6_CS0/DDR6_CA3
DDR1_PAR/DDR7_CS1/DDR7_CS0/DDR7_CA3
DDR1_ALERT#
DDR1_VREF_CA
TGL_U_IP_EXT
4 3
2
CLOCK
R41
M_B_CLK_DDR1 [15]
R42
M_B_CLK_DDR#1 [15]
M52
M53
AC42
AC41 DIFF=85ohm
Y52
M_B_CLK_DDR0 [15]
Y53
M_B_CLK_DDR#0 [15]
R47
R45
K51
K53
AC47
AC45
W51
W53
P52
M_B_CKE1 [15] CTRL
J50
M_B_CKE0 [15]
AE42
M_B_CS#1 [15]
AE47 SINGLE=45ohm
M_B_CS#0 [15]
N42
N45
N44
N47
J53
AC50
AC53
M_B_DQS[7:0] [15]
M_B_DQS7
K36
STROBE
K38 M_B_DQS#7
M_B_DQS#[7:0] [15]
M_B_DQS6
G44
M_B_DQS#6 M_B_DQS#0
J44
M_B_DQS5 M_B_DQS#1
D39
M_B_DQS#5 M_B_DQS#2
C39 DIFF=90ohm
C45 M_B_DQS4 M_B_DQS#3
M_B_DQS#4 M_B_DQS#4
D45
M_B_DQS3 M_B_DQS#5
AJ44
M_B_DQS#3 M_B_DQS#6
AL44
AV44 M_B_DQS2 M_B_DQS#7
M_B_DQS#2
AR44
M_B_DQS1
AG51
M_B_DQS#1
AG50
M_B_DQS0
AN51
AN50 M_B_DQS#0
AE44
CTRL
M_B_ODT1 [15]
AE45 SINGLE=45ohm
M_B_ODT0 [15] M_B_A[16:0] [15]
M_B_A16
AA47
M_B_A15
AA44
M_B_A14
AA45
M_B_A13
AE41
P53 M_B_A12
CMD
M_B_A11
N51
M_B_A10
U42
M_B_A9
P50
U53 M_B_A8
SINGLE=45ohm
M_B_A7
W50
M_B_A6
U52
M_B_A5
U50
M_B_A4
AA51
AA53 M_B_A3
M_B_A2
U47
M_B_A1
AC52
M_B_A0
U41
K50
M_B_BG1 [15]
J52
M_B_BG0 [15]
AA42
M_B_BA1 [15]
U44
M_B_BA0 [15]
N53
M_B_ACT# [15]
U45
DDR1_B_PARITY [15]
AU53
DDR1_B_ALERT# [15]
AU52
DDR1_VREF_CA [15]
SINGLE=50ohm
Title Title Title
[04] TGL U -C / DDR CHB [04] TGL U -C / DDR CHB [04] TGL U -C / DDR CHB
Size Size Size Document Number Document Number Document Number
6-71-NLx0MU-D02 6-71-NLx0MU-D02 6-71-NLx0MU-D02
A3 A3 A3
Date: Date: Date: W ednesday, August 18, 2021 W ednesday, August 18, 2021 W ednesday, August 18, 2021
2
Schematic Diagrams
1
D
Sheet 4 of 47
C
Processor 3/12
B
A
R e v R e v R e v
D02 D02 D02
A0
Sheet Sheet Sheet 4 4 4 o f o f o f 47 47 47
1
Processor 3/12 B - 5