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Schematic Diagrams
RTL8411B
D
Sheet 39 of 47
C
LAN I219-LM
B
A
B - 40 RTL8411B
5
4
GIGA LAN (INTEL LAN I219)
LAN i219
LAN_BD_FOR_14"
YR3
[42]
Y_CLK_PCIE_GLAN
LAN_BD_FOR_14"
YR4
[42]
Y_CLK_PCIE_GLAN#
LAN_BD_FOR_14"
YUC5
[42]
Y_PCIE_RXP7_GLAN
LAN_BD_FOR_14"
YUC6
[42]
Y_PCIE_RXN7_GLAN
LAN_BD_FOR_14"
YUC7
[42]
Y_PCIE_TXP7_GLAN
LAN_BD_FOR_14"
YUC8
[42]
Y_PCIE_TXN7_GLAN
[42]
Z_CLK_PCIE_GLAN
[42]
Z_CLK_PCIE_GLAN#
SMBUS PULL-UP OPTIONS
[42]
Z_PCIE_RXP7_GLAN
SMBUS SPEED
[42]
Z_PCIE_RXN7_GLAN
1MHz(Defaul
setting)
499ohm
100KHz/400KHz
2.2Kohm
[42]
Z_PCIE_TXP7_GLAN
[42]
Z_PCIE_TXN7_GLAN
ZR12
*499_1%_04
U_VDD3
ZR9
*499_1%_04
NOTE: Default SMBus
[42]
Z_SML0_CLK
Address is 0xC8
[42]
Z_SML0_DATA
ZR26
ZR25
[42]
Z_LAN_WAKEUP#_R
NOTE: LANWAKE_N must be
ZR18
3.3V_LAN
connected to PCH's GPIO27.
ZR19
ZR16
[42]
Z_LAN_DISABLE#
NOTE: LAN_DISABLE_N must be connected
to PCH's GPIO12/LAN_PHY_PWR_CTRL.
ZR17
This GPIO12 pin must be set as
3.3V_LAN
ZR13
"LAN_PHY_PC" function through FITC
tool.
DESIGN NOTE: PCH's LANPHYPC output
ZT1
does not require pull-up. Resistors are no-stuff (for testing
ZT2
purpose only).
ZT3
ZT4
Crystal
503 2 SI Z E
ZR11
0_04
ZX1
1
2
DESIGN NOTE: C7 & C8 value may vary depending on the
actual Cstray of the board. Cstray is varied because
specific board stack-up, layout, etc. For examples:
4
3
Using Cload=18pF Crystal part, if Cstray=7pF then
ZC12
ZC11
C7=C8=22pF and if Cstray=6pF then C7=C8=24pF.
19001-X-016-3
Cload=[(C7*C8)/(C7+C8)] + Cstray.
Each design should measure the crystal' s ppm to make
sure it is within the I217 Specification.
B Y
6-22-25R00-1BV
6-22-25R00-1B4
6-22-25R00-1B5
modify,0605
max
U53
U40
SB
LAN
Q370 MP
N350TV
I219LM MP
VPRO
6-03-00370-0F2
6-03-00219-030
N350TW
H370 MP
I219V MP
non-VPRO
6-03-00370-0F0
6-03-00219-031
5
4
3
U_VDD3
The 10Kohm pull-up resistor of CLK_REQ_N is required
to either 3.3V Suspend (5, 6, 7) or Core (2) rail,
depending on the power well of PCH's input PCIECLKRQx#
buffer. See Platform Design Guide for more details
CLK_PCIE_C_GLAN
0_02
ZR20
CLK_PCIE_C_GLAN#
0_02
10K_04
0.1u_6.3V_X5R_02
PCIE_RXP7_C_GLAN
PCIE_RXN7_C_GLAN
0.1u_6.3V_X5R_02
PCIE_TXP7_C_GLAN
0.1u_6.3V_X5R_02
ZZ1
PCIE_TXN7_C_GLAN
0.1u_6.3V_X5R_02
48
[42]
Z_GLAN_CLKREQ#
CLK_REQ_N
36
[40,42]
Z_BUF_PLT_RST#
PE_RST_N
CLK_PCIE_C_GLAN
ZR22
0_02
LAN_BD_FOR_15"
44
CLK_PCIE_C_GLAN#
PE_CLKP
ZR23
0_02
LAN_BD_FOR_15"
45
PE_CLKN
PCIE_RXP7_C_GLAN
ZC13
0.1u_6.3V_X5R_02
LAN_BD_FOR_15"
38
PCIE_RXN7_C_GLAN
PETp
ZC14
0.1u_6.3V_X5R_02
LAN_BD_FOR_15"
39
PETn
PCIE_TXP7_C_GLAN
41
ZC15
0.1u_6.3V_X5R_02
LAN_BD_FOR_15"
PCIE_TXN7_C_GLAN
PERp
ZC16
0.1u_6.3V_X5R_02
LAN_BD_FOR_15"
42
PERn
28
SMB_CLK
31
SMB_DATA
4.7K_04
U_VDD3
LAN_WAKE_N
0_04
2
LANWAKE_N
LAN_DISABLE_N
*10K_04
3
LAN_DISABLE_N
0_04
*10K_04
26
LED0
27
LED1
25
LED2
*10K_04
*10K_04
LAN_JTAG_TDI
32
LAN_JTAG_TDO
JTAG_TDI
34
LAN_JTAG_TMS
JTAG_TDO
33
LAN_JTAG_TCK
JTAG_TMS
35
JTAG_TCK
LAN_XTAL_OUT
9
LAN_XTAL_IN
XTAL_OUT
10
XTAL_IN
LAN_TEST_EN
30
TEST_EN
RES_BIAS
12
RBIAS
ZR10
ZR7
I219V MP
1K_04
3.01K_1%_04
1ZR1
*0_02
4ZR1
*0_02
LAN_BD
LAN_BD
2ZR1
*0_02
5ZR1
*0_02
LAN_BD
LAN_BD
3ZR1
*0_02
6ZR1
*0_02
LAN_BD
LAN_BD
7ZR1
*0_02
8ZR1
*0_02
LAN_BD
LAN_BD
U55
U54
MX25L25673GM2I-08G
N/A
6-04-XXXXX-XXX
ME+Bios
W25Q128JVSIQ
N/A
6-04-25128-A74
ME+Bios+EC
3
2
1
Z_LAN_MDIP0
13
MDI_PLUS0
Z_LAN_MDIN0
Z_LAN_MDIP0
[41]
14
MDI_MINUS0
Z_LAN_MDIN0
[41]
Z_LAN_MDIP1
17
Z_LAN_MDIP1
[41]
MDI_PLUS1
Z_LAN_MDIN1
18
Z_LAN_MDIN1
[41]
MDI_MINUS1
Z_LAN_MDIP2
20
MDI_PLUS2
Z_LAN_MDIN2
Z_LAN_MDIP2
[41]
21
MDI_MINUS2
Z_LAN_MDIN2
[41]
23
Z_LAN_MDIP3
3.3V_LAN
Z_LAN_MDIP3
[41]
MDI_PLUS3
Z_LAN_MDIN3
24
Z_LAN_MDIN3
[41]
MDI_MINUS3
SVR_EN_N
ZR14
0_04
6
ZR15
*4.7K_04
ZC8
ZC9
SVR_EN_N
1
ZR21
4.7K_04
3.3V_LAN
RSVD_VCC3P3
5
ZC10 1u_6.3V_X5R_02
VDD3P3_5
4
VDD3P3_4
15
VDD3P3_15
19
VDD3P3_19
29
VDD3P3_29
8
0.9V_LAN_M
VDD0P9_8
11
VDD0P9_11
16
LAYOUT NOTE: Place L, C*3 and
R close to PHY
VDD0P9_16
NOTE: Total requirement Cout>=20uF. ESR<50mohm.
22
VDD0P9_22
37
VDD0P9_37
Keep
short
40
VDD0P9_40
and wide
43
VDD0P9_43
46
modify,0510
max
VDD0P9_46
47
VDD0P9_47
ZL6
CTRL_0P9
7
CTRL_0P9
49
SWF2520CF-4R7M-M
ZC2
ZC4
ZC5
GND_EPAD
Title
Title
Title
[39] INTEL LAN i219-LM(Sub Board)
[39] INTEL LAN i219-LM(Sub Board)
[39] INTEL LAN i219-LM(Sub Board)
Size
Size
Size
Document Number
Document Number
Document Number
R e v
R e v
R e v
6-71-NLx0MU-D02
6-71-NLx0MU-D02
6-71-NLx0MU-D02
D02
D02
D02
Custom
Custom
Custom
Date:
Date:
Date:
Wednesday, August 18, 2021
Wednesday, August 18, 2021
Wednesday, August 18, 2021
Sheet
Sheet
Sheet
39
39
39
o f
o f
o f
47
47
47
2
1
D
C
B
A
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