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SUPER P6DLS/P6DLE/P6SLS/P6SLA User's Manual
1-4 Chipset Overview
The 440LX chipset is developed by Intel as the ultimate Pentium II
processor platform targeted for emerging 3D graphics and multi-
media applications.
with optimized DRAM controller and data path, the chipset intro-
duces the Accelerated Graphics Port (AGP) interface. AGP is a high
performance, component level interconnect targeted at 3D applica-
tions and is based on a set of performance enhancements to PCI.
The I/O subsystem portion of the 440LX platform is based on the
PIIX4, a highly integrated version of Intel's PCI-to-ISA bridge family.
The 440LX PCI/AGP Controller (PAC) system bus interface supports
up to two Pentium II processors.
DRAM interface (64-bit data plus ECC).
3.3V DRAM technologies. The PAC provides the interface to a PCI
bus operating at 33 MHz.
ant with the PCI Rev 2.1 Specification. The AGP interface is based
on the AGP Specification Rev 1.0.
(532 MB/s) data transfer rates.
1-5 Wake-On-LAN (WOL)
Wake-on-LAN is defined as the ability of a management application
to remotely power up a computer which is powered off. Remote PC
setup, updates, and asset tracking can occur after hours and on
weekends so daily LAN traffic is kept to a minimum and users are
not interrupted.
The motherboards have a 3-pin header (WOL) used to connect to
the 3-pin header on the Network Interface Card (NIC) which has
WOL capability.
1-6 Power Supply
As with all computer products, a stable power source is necessary
for proper and reliable operation. It is even more important for high
Along with System-to-PCI bridge integrated
It provides an optimized 72-bit
This interface supports
This interface implementation is compli-
It can support up to 133 MHz
1-22
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Table of Contents
Troubleshooting
