Table of Contents
Advertisement
1-2
Chipset Overview (Intel's E7210 Canterwood
Chipset)
The E7210 Canterwood Chipset contains the following main components:
the E7210 Canterwood Memory Controller Hub (MCH) and the I/O Controller
Hub 5(ICH5R).
face.
Memory Controller Hub (MCH)
The E7210 Canterwood Memory Controller Hub (MCH) is designed to sup-
port Intel PGA 478-pin Processors. The function of the E7210 Canterwood
MCH is to arbitrate the flow of data transfer
system memory, and
MHz FSB, 400/333 Memory Interface, 533 MHz FSB, 333/266 Memory Inter-
face, and 400 MHz FSB 266 MHz Memory Interface.
System Memory Interface
The E7210 Canterwood Memory Controller (MCH) supports two 64-bit wide
DDR data channels with bandwidth up to 6.4 GB/s (DDR400) in dual channel
mode. It supports 128-Mb, 256-Mb,512-Mb, x8, X16 DDR. Maximum system
memory supports up to 4.0 GB for Dual-Channel. ECC/Non ECC unbuffered
DDR DIMMs are supported, but it does not support registered, mixed-mode
DIMMs.
Intel ICH5R System Features
The I/O Controller Hub provides the I/O subsystem with access to the rest
of the system. It supports 2-channel Ultra ATA/100 Bus Master IDE Control-
ler, two Serial ATA (SATA) Host Controllers, SMBus 2.0 Controller, LPC/
Flash BIOS Interface, PCI 2.3 Interface, and Integrated System Management
Controller.
These two components are interconnected via Hub Inter-
Hub Interface. The Canterwood MCH supports 800
1-13
Chapter 1: Introduction
between system bus (FSB),
Advertisement
Table of Contents
