AOC Vibrant VL7A9DA Service Manual page 55

Figure 7. timing Diagrams of the TFT Panel Interface (One pixel per clock)
(a) Vertical size in TFT
PVS
PHS
(b) Vsync width and display position in TFT
PDE
PVS
t18
PHS
(c) Horizontal size in TFT RGBs
PHS
PCLK
PDE
RGB data from
data paths
(d) Hsync width in TFT
t14
t3
t4
t19
t12
Panel Background Color Displayed
t13
t16
t15
t1
t5
t6
t7
t11
t10
t2
t10
t8
t9
t16