AOC Vibrant VL7A9DA Service Manual page 56

(a) Two pixel per clock mode in TFT
PDE
t16
PCLK
ER R0,(N:0)
EG
G0,(N:0)
EB
OR R1,(N:0)
OG
(b) One pixel per clock mode in TFT
OB
PDE
t1
6
PCLK
R(n:0
R0
)
G(n:0
G0
)
B(n:0
B0
)
2.6.2 Power Manager
LCD panels require logic power, panel bias power, and control signals to be sequenced in a specific order, otherwise
severe damage may occur and disable the panel permanently. The gmZAN1 has a built in power sequencer (Power
Manager) that prevents this kind of damage.
The Power Manager controls the power up/down sequences for LCD panels within the four states described below.
See the timing diagram Figure 9.
Figure 8. Data latch timing of the TFT Panel Interface
B0,(N:0)
G1,(N:0)
B1,(N:0)
t1
3
t1
4
R1
t13
t15
t14
R2,(N:0)
G2,(N:0)
B2,(N:0)
R3,(N:0)
G3,(N:0)
B3,(N:0)
t1 t1
5 7
t1
6
t16 t17
R4,(N:0)