AOC Vibrant VL7A9DA Service Manual page 54

Signal Name
PVS Period
Frequency
Front porch
Back porch
Pulse width
PdispE
Disp. Start from VS
PVS set up tp PHS
PVS hold from PHS
PHS Period
Front porch
Back porch
Pulse width
PdispE
Disp. Start fom HS
PCLKA, Frequency
PCLKB*4
Clock (H) *2
Clock (L) *2
Type
Data Set up *3
Hold *3
width
NOTE: Numbers in [ ] are for two pixels/clock mode.
NOTE: The drive current of the panel interface signals is programmable as shown in Table 1. The drive current is to be
programmed through the API upon chip initialization. Output current is programmable from 2 mA to 20mA in increments of 2 mA.
Drive strength should be programmed to match the load presented by the cable and input of the panel. Values shown are based on a
loading of 20pF and a drive strength of 8 mA.
NOTE *1: The PCLK is the panel shift clock.
NOTE *2: The DCLK stands for Destination Clock (DCLK) period. Is equal to:
-PCLK period in one pixel/clock mode,
-twice the PCLK period in two pixels/clock mode.
NOTE *3: The setup/hold time spec. for PCLK also applies to PHS and PdispE. The setup time (t16) and the hold time (t17) listed
in this table are for the case in which no clock-to-data skew is added. The PVS/PHS/PdispE/Pdata signals are asserted on
the rising edge of the PCLK. The polarity of the PCLK and its skew are programmable. Clock to Data skew can be
adjusted in sixteen 800-ps increments. In combination with the PCLK polarity inversion, the clock-to-data phase can be
adjusted in total of 31 steps.
NOTE *4: The polarity of the PCLKA and the PCLKB are independently programmable.
The micro controller must have all the timing parameters of the panel used for the monitor. The parameters are to be
stored in a non-volatile memory. As can be seen from this table, the wide range of timing programmability of the
gmZAN1 panel interface makes it possible to support various kinds of panels known today:
Table 13. gmZAN1 TFT Panel Interface Timing
Min
t1 0
t2 0
t3 0
t4 0
t5 0
t6 0
t18 1
t19 1
t7 0
t8 0
t9 0
t10 0
t11 0
t12 0
t13
t14 DCLK/2-3 [DCLK-3]
t15 DCLK/2-3 [DCLK-3]
-
t16 DCLK/2-5 [DCLK-5]
t17 DCLK/2-5 [DCLK-5]
3 bits
Typical Max
16.67 2048
-
60 -
2048
2048
2048
Panel height 2048
2048
2048
2048
2048 [1024
2048
2048
2048
Panel width 2048 [1024]
2048
120 [60]
DCLK/2-2 [DCLK-2]
DCLK/2-2 [DCLK-2]
One pxl/clock -
[two pxl/clock]
DCLK/2-2 [DCLK-2]
DCLK/2-2 [DCLK-2]
18 bits [36 bits] 24 bits [48 bits]
Unit
lines
ms
Hz
lines
lines
lines
lines
lines
PCLK *1
PCLK *1
PCLK *1
PCLK *1
PCLK *1
PCLK *1
PCLK *1
PCLK *1
MHz
ns
ns
ns
ns
bits/pixel