AOC Vibrant VL7A9DA Service Manual page 41

PIN # Name
125 DVDD
127 DAC_DGNDA
128 DAC_DVDDA
129 PLL_DVDDA
130 Reserved
131 PLL_DGNDA
132 SUB_DGNDA
133 SUB_SGNDA
134 PLL_SGNDA
135 Reserved
136 PLL_SVDDA
137 DAC_SVDDA
138 DAC_SGNDA
139 SVDD
141 TCLK
142 XTAL
143 PLL_RVDDA
144 PLL_RGNDA
145 Reserved
146 SUB_RGNDA
148 VSYNC
149 SYN_VDD
150 HSYNC/CSYNC
Table 3 : Clock Recovery / Time Base Conversion
I/O Description
Digital power for Destination DDS (direct digital synthesizer). Must be bypassed
with a 0.1uF capacitor to digital ground plane.
Analog ground for Destination DDS DAC. Must be directly connected to the
analog system ground plane.
Analog power for Destination DDS DAC. Must be bypassed with a 0.1uF
capacitor to pin 127 (DAC_DGNDA).
Analog power for the Destination DDS PLL. Must be bypassed with a 0.1uF
capacitor to pin 131 (PLL_DGNDA).
For testing purposes only. Do not connect.
Analog ground for the Destination DDS PLL. Must be directly connected to the
analog system ground plane.
Dedicated pin for the substrate guard ring that protects the Destination DDS.
Must be directly connected to the analog system ground plane.
Dedicated pin for the substrate guard ring that protects the Source DDS. Must be
directly connected to the analog system ground plane.
Analog ground for the Source DDS PLL. Must be directly connected to the
analog system ground.
For testing purposes only. Do not connect.
Analog power for the Source DDS DAC. Must be bypassed with a 0.1uF
capacitor to pin 134 (PLL_SGNDA)
Analog power for the Source DDS DAC. Must be by passed with a 0.1uF
capacitor to pin 138 (DAC_SGNDA)
Analog power for the Source DDS DAC. Must be directly connected to the
analog system ground.
Digital power for the Source DDS. Must be bypassed with a 0.1uF capacitor to
digital ground plane.
I Reference clock(TCLK) input from the 50 MHz crystal oscillator
O If using an external oscillator, leave this pin floating. If using an external crystal,
connect crystal between TCLK(141) and XTAL(142). See MFB5(pin 107).
Analog power for the Reference DDS PLL. Must be bypassed with a 0.1uF
capacitor to pin 144(PLL_RGNDA)
Analog ground for the Reference DDS PLL. Must be directly connected to the
analog system ground plane.
For testing purposes only. Do not connect.
Dedicated pin for the substrate guard ring that protects the Reference DDS. Must
be directly connected to the analog system ground plane.
I CRT Vsync input. TTL Schmitt trigger input.
Digital power for CRT Sync input.
I CRT Hsync or CRT composite sync input. TTL Schmitt trigger input.