AOC Vibrant VL7A9DA Service Manual page 52

The display start/end registers store the first and the last pixels/lines of the last frame that have RGB data above a
programmed threshold.
The reference point of the STM block is the same as that of the source timing generator (STG) block:
l
The first pixel: the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low to high.
l
The first line: the line whose HSYNC rising edge sees the transition of the VSYNC polarity from low to high.
The CRC data and the line data are used to detect a test pattern image sent to the gmZAN1 input port.
2.4.2 IRQ Controller
Some input timing conditions can cause the gmZAN1 chip to generate an IRQ. The IRQ-generating conditions are
programmable, as given in the following table.
IRQ Event
Timing Event
Timing Change
Reading the IRQ status flags will not affect the STM registers.
Note that if a new IRQ event occurs while the IRQ status register is being read, the IRQ signal will become inactive
for minimum of one TCLK period and then get re-activated. The polarity of the IRQ signal is programmable.
2.5 Data Path
The data path block of gmZAN1 is shown in Figure 6.
Sampled Data
8
(or from
pattern
generator
Table 12. IRQ-Generation Conditions
Figure 6. gmZAN1 Data Path
8
Scaling Gamma
Filter Table
Remark
One of the three events:
l
Leading edge of Vsync input,
l
Panel line count (the line count is programmable),
l
Every 10ms
Only one event may be selected at a time.
Any of the following timing changes:
l
Sync loss,
l
DDS tracking error beyond threshold,
l
Horizontal/vertical timing change beyond threshold
Threshold values are programmable.
10 Panel
RGB
Data
Offset
Dither
Background
Color
Internal
OSD
External
OSD
8 or 6
1
0
1
S
0
1
S
0
S
8 or 6
Panel
Data