Revision History - Xilinx KC705 User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
01/23/12 1.0
04/05/12 1.1
12/10/12 1.2
KC705 Evaluation Board
Initial Xilinx release.
Updated links from Table 1-1, page
description under FPGA Configuration, page
page 12 and Table 1-4, page
page 25. Added link to Si570 device vendor on
LEDs, page 49 and Figure 1-24, page
page 54 and added Figure 1-32, page
page 56 and Table 1-28, page 57
module cooling requirement to
Control, page 66. Updated
Added Appendix E, Compliance with European Union Directives and
Appendix D, Board Setup, and
Replaced direct, inline links to external references in the body text with indirect
references to the links in a numbered list in
the value for frequency jitter for the
information for SFP_RS1, page 38
Appendix F, Additional Resources.
www.xilinx.com
Revision
10. Revised the JTAG configuration mode USB cable
11. Added
13. Added links to User SMA Clock Input in
page
49. Updated Power On/Off Slide Switch SW15,
55. Revised FPGA Mezzanine Card Interface,
and Table 1-29, page
Power Management, page
Table 1-35, page 71. Added references to
Appendix E, Board Specifications.
Appendix F, Additional
System Clock Source, page
in Table 1-15. Revised contents and organization of
Encryption Key Backup Circuit,
Table 1-8,
27. Added Ethernet PHY Status
62. Added description of power
63. Added Cooling Fan
Documents, page
Standards,
Resources. Revised
26. Revised jumper
UG810 (v1.4) July 18, 2013
85.