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Table 15-5. READY Signal Timing Definitions (Continued)
Symbol
††
T
READY Hold after ALE Low
LLYX
Minimum time the level of the READY signal must be valid after ALE falls. If the maximum
value is exceeded, additional wait states will occur.
††
T
ALE Low to READY Setup
LLYV
Maximum time the external device has to deassert READY after ALE falls.
T
Data Valid to WR# High
QVWH
Time between data being valid on the bus and the microcontroller deasserting WR#.
T
RD# Low to Input Data Valid
RLDV
Maximum time the memory system has to output valid data after the microcontroller asserts
RD#.
T
RD# Low to RD# High
RLRH
RD# pulse width.
T
WR# Low to WR# High
WLWH
WR# pulse width.
T
1/F
1
1
XTAL
XTAL
All AC timings are referenced to T
†
This specification applies to the 8XC196MC, MD microcontrollers only.
††
This specification applies to the 8XC196MH microcontroller only.
15.5 BUS-CONTROL MODES
The ALE and WR bits (CCR0.3 and CCR0.2) define which bus-control signals will be generated
during external read and write cycles. Table 15-6 lists the four bus-control modes and shows the
CCR0.3 and CCR0.2 settings for each.
.
Bus-control Mode
Standard Bus-control Mode
Write Strobe Mode
Address Valid Strobe Mode
Address Valid with Write Strobe Mode
Definition
.
1
XTAL
Table 15-6. Bus-control Modes
Bus-control Signals
ALE, RD#, WR#, BHE#
ALE, RD#, WRL#, WRH#
ADV#, RD#, WR#, BHE#
ADV#, RD#, WRL#, WRH#
Get other manuals https://www.bkmanuals.com
INTERFACING WITH EXTERNAL MEMORY
CCR0.3
CCR0.2
(ALE)
(WR)
1
1
1
0
0
1
0
0
15-21
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