Intel 8XC196MC User Manual page 534

USFR
The unerasable PROM (USFR) register contains two bits that disable external fetches of data and
instructions and another that detects a failed oscillator. These bits can be programmed, but cannot be
erased.
WARNING: These bits can be programmed, but can never be erased. Programming these bits makes
dynamic failure analysis impossible. For this reason, devices with programmed UPROM bits cannot
be returned to Intel for failure analysis.
7
— —
Bit Bit
Number Mnemonic
7:4 —
3 DEI
2 DED
1:0 —
— —
Reserved; for compatibility with future devices, write zeros to these bits.
Disable External Instruction Fetch
Setting this bit prevents the bus controller from executing external
instruction fetches. Any attempt to load an external address initiates a
reset.
Disable External Data Fetch
Setting this bit prevents the bus controller from executing external data
reads and writes. Any attempt to access data through the bus controller
initiates a reset.
Reserved; for compatibility with future devices, write zero to these bits.
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Address:
Reset State (MC, MD):
Reset State (MH):
DEI DED
Function
REGISTERS
USFR
1FF6H
02H
XXH
0
— —
C-57