Edge-Aligned Modes - Intel 8XC196MC User Manual

8XC196MC, MD, MH USER'S MANUAL
WG_COMP x
WG_COUNTER
1
WG_COUNTER
=WG_COMP x
WG Interrupt
P6.0 / WG1#
P6.1 / WG1
Mode 0, OP0 = OP1 = 1, PH1.0 = PH1.1 = PH1.2 = 1
Figure 9-5. Center-aligned Modes — Output Operation
9.3.5.2

Edge-Aligned Modes

In the edge-aligned modes, the counter begins at 1 and counts up to the WG_RELOAD value.
When you write to the WG_RELOAD register, WG_COUNTER is loaded with 0001H. When
you set the enable bit in the control register, the counter begins counting up and continues count-
ing until it reaches the WG_RELOAD value or, in mode 3 only, until an EPA event occurs. At
this point, WG_COUNTER is reloaded with 0001H and WG_RELOAD is updated, so a new re-
load value takes effect for the next cycle. The counter resumes counting up from 0001H to
WG_RELOAD. This produces a smoothly ascending count, illustrated by the sawtooth wave in
Figure 9-6, with a period that is equal to the WG_RELOAD value. Figure 9-7 shows the operation
of outputs and interrupts in edge-aligned modes.
In mode 2, the registers are updated only once during the carrier period, when the counter reaches
the reload value. In mode 3, the registers are also updated when an EPA peripheral function event
occurs. (You must configure an EPA channel for this function. See Chapter 11, "Event Processor
Array (EPA)" for information.)
9-10
Note:
Carrier period and duty cycle both
change since WG_COMP
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is not changed.
x
= Additional interrupt in mode 1 only.
A2641-01