Intel 8XC196MC User Manual page 242

Table 11-2. EPA and Timer/Counter Signals (Continued)
Port Pin
8XC196MC 8XC196MD
P2.4 P2.4
P2.5 P2.5
P2.6 P2.6
P2.7 P2.7
— P7.2
— P7.3
Mnemonic
MC
COMP0_CON 1F58H
COMP1_CON 1F5CH
COMP2_CON 1F60H
COMP3_CON 1F64H
COMP4_CON —
COMP5_CON —
COMP0_TIME 1F5AH
COMP1_TIME 1F5EH
COMP2_TIME 1F62H
COMP3_TIME 1F66H
COMP4_TIME —
COMP5_TIME —
EPA0_CON 1F40H
EPA1_CON 1F44H
EPA2_CON 1F48H
EPA3_CON 1F4CH
EPA4_CON —
EPA5_CON —
EPA0_TIME 1F42H
EPA1_TIME 1F46H
EPA2_TIME 1F4AH
EPA3_TIME 1F4EH
EPA4_TIME —
EPA5_TIME —
INT_MASK 0008H
INT_MASK1 0013H
EPA
Signals
8XC196MH
P2.4 COMP0
P2.5 COMP1
P2.6 COMP2
P2.3 COMP3
— COMP4
— COMP5
Table 11-3. EPA Control and Status Registers
Address
MD MH
1F58H 1F58H
1F5CH 1F5CH
1F60H 1F60H
1F64H 1F4CH
1F68H —
1F6CH —
1F5AH 1F5AH
1F5EH 1F5EH
1F62H 1F62H
1F66H 1F4EH
1F6AH —
1F6EH —
1F40H 1F40H
1F44H 1F44H
1F48H —
1F4CH —
1F50H —
1F54H —
1F42H 1F42H
1F46H 1F46H
1F4AH —
1F4EH —
1F52H —
1F56H —
0008H 0008H
0013H 0013H
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EVENT PROCESSOR ARRAY (EPA)
EPA
Signal
Type
O Output of the compare-only channels.
Description
EPA x Compare Control
These registers control the functions of the
compare-only channels.
EPA x Compare Time
These registers contain the time at which an event
is to occur on the compare-only channels.
EPA x Capture/Compare Control
These registers control the functions of the
capture/compare channels. EPA1_CON and
EPA3_CON require an extra byte because they
contain an additional bit for PWM remap mode.
These two registers must be addressed as words;
the others can be addressed as bytes.
EPA x Capture/Compare Time
In capture mode, these registers contain the
captured timer value. In compare mode, these
registers contain the time at which an event is to
occur. In capture mode, these registers are
buffered to allow two captures before an overrun
occurs. However, they are not buffered in compare
mode.
Interrupt Mask
The bits in this 8-bit register enable and disable
(mask) the interrupts associated with the corre-
sponding bits in the INT_PEND register.
Interrupt Mask 1
The bits in this 8-bit register enable and disable
(mask) the interrupts associated with the corre-
sponding bits in the INT_PEND1 register.
Description
11-3