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Chapter 1: VC709 Evaluation Board Features
Table 1-20: VITA 57.1 FMC HPC J35 Connections to FPGA U1 (Cont'd)
J35 FMC
Schematic Net Name
HPC Pin
J21
FMC1_HPC_HA22_P
J22
FMC1_HPC_HA22_N
J24
FMC1_HPC_HB01_P
J25
FMC1_HPC_HB01_N
J27
FMC1_HPC_HB07_P
J28
FMC1_HPC_HB07_N
J30
FMC1_HPC_HB11_P
J31
FMC1_HPC_HB11_N
J33
FMC1_HPC_HB15_P
J34
FMC1_HPC_HB15_N
J36
FMC1_HPC_HB18_P
J37
FMC1_HPC_HB18_N
J39
FMC1_VIO_B_M2C
Notes:
1. FMC1_VIO_B_M2C is sourced by a FMC card which supports the HB bus, when plugged onto the HPC connector J35.
2. FMC1_VIO_B_M2C is a variable voltage but it cannot exceed the fixed VADJ 1.8V value.
Power Management
[Figure
The VC709 board power distribution diagram is shown in
The PCB layout and power system have been designed to meet the recommended criteria
described in 7 Series FPGAs PCB Design and Pin Planning Guide (UG483).
54
U1 FPGA Pin
F36
F37
H28
H29
G26
G27
K22
J22
M21
L21
G21
G22
(1) (2)
NA
1-2, callout 26]
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J64 FMC
Schematic Net Name
HPC Pin
K20
FMC1_HPC_HA21_N
K22
FMC1_HPC_HA23_P
K23
FMC1_HPC_HA23_N
K25
FMC1_HPC_HB00_CC_P
K26
FMC1_HPC_HB00_CC_N
K28
FMC1_HPC_HB06_CC_P
K29
FMC1_HPC_HB06_CC_N
K31
FMC1_HPC_HB10_P
K32
FMC1_HPC_HB10_N
K34
FMC1_HPC_HB14_P
K35
FMC1_HPC_HB14_N
K37
FMC1_HPC_HB17_CC_P
K38
FMC1_HPC_HB17_CC_N
K40
FMC1_VIO_B_M2C
Figure
U1 FPGA
Pin
D38
A35
A36
J25
J26
K23
J23
M22
L22
J21
H21
M24
L24
NA
1-24.
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
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