5.2
Address space and address assignment
The CPU and TM NPU exchange their data via the process image.
The TM NPU works with a process image of 256 bytes for inputs and 256 bytes for outputs.
In the process image of the inputs and outputs, the first two bytes are always reserved for the
control, status and error information.
You can use all other addresses for communication and data transfer with the running
application (app).
• PII: Byte 0 = Status information
• PII: Byte 1 = Error information
• PIQ: Bytes 0 and 1 = Control information
Address assignment in the process image input (PII)
The figure below shows the assignment of the address space for the configuration with 256
bytes for inputs.
You can freely assign the start addresses.
IB n
IB n +1
IB n +2
IB n +255
Address assignment in the process image output (PIQ)
The figure below shows the assignment of the address space for the configuration with 256
bytes for outputs.
You can freely assign the start addresses.
QB n
QB n +1
QB n +2
QB n +255
Technology Module TM NPU
Equipment Manual, 07/2023, A5E46384784-AC
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
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7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
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7 6 5 4 3 2 1 0
5.2 Address space and address assignment
Input value:
Byte 0: Status information
Byte 1: Error information
User data
:
.
User data
Output value:
Control byte 0
Control byte 1
User data
:
.
User data
Configuration / address space
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