Quick-Setup Test Result - Texas Instruments ADS62P EVM Series User Manual

Connecting to FPGA Platforms
4.1.1 Quick-Test Results
The user can make the jumper setting as mentioned in
external clock source from J19 and a direct input signal J6 (Channel A) or J3 (Channel B) to the ADC.
This setup uses Power Option 2
which is the default on the EVM.
input signal of a 57.6-MHz frequency and clock frequency of 250 MHz with ADS62PXX.
22 ADS62PXXEVM
Table
(Table 3), Analog Input Option 1
Figure 10 shows the ADC performance capture using TSW1200 with the
Figure 10. Quick-Setup Test Result
1. In this configuration, the EVM uses an
(Table 5), and Clock Option 1
SLAU237A – May 2008 – Revised April 2009
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(Table 7),