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4.1.2
Test Result With Onboard VCXO and Clock Through Crystal Filter
This test uses the VCXO of frequency 983.04 MHz. This setup uses the Power Option 2
Input Option 1
(Table
was chosen to provide the clock to the ADC. The CDCE72010 provides a single-ended clock through
output Y0
(Table
7), which is passed through a crystal filter of center frequency 245.76 MHz. This was the
example setup; the VCXO and the crystal filter are not populated on the EVM because the values depend
on the end application sampling rate. The capture result for ADS62PXX is as shown in
Figure 11. ADC Performance With Clock Through Onboard VCXO, CDCE72010 and Crystal Filter
SLAU237A – May 2008 – Revised April 2009
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5), and Clock Option 2
(Table
7). For this test, the CDCE72010 crystal filter path
Connecting to FPGA Platforms
(Table
3), Analog
Figure
11.
ADS62PXXEVM
23
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