Attach The Gth Quad Connector - Xilinx IBERT ML628 Getting Started Manual

Transmitter pairs TX0 and TX1 on Quad 116 are not connected to the BullsEye connector
pads. Refer to UG771, ML628 Virtex-6 FPGA GTX and GTH Transceiver Characterization
Board User Guide for details on accessing these signals.
The SuperClock-2 module provides LVDS clock outputs for the GTH and GTX transceiver
reference clocks in the IBERT demonstrations.
differential clock SMA connectors on the clock module which can be connected to the
reference clock cables. The four SMA pairs labeled CLKOUT provide LVDS clock outputs
from the Si5368 clock multiplier/jitter attenuator device on the clock module. The SMA
pair labeled Si570_CLK provides LVPECL clock output from the Si570 programmable
oscillator on the clock module. For the GTH IBERT demonstration, the output clock
frequencies are preset to 174.690 MHz. For more information regarding the SuperClock-2
module, refer to UG770, HW-CLK-101-SCLK2 SuperClock-2 Module User Guide.
Note:
board.
X-Ref Target - Figure 1-3
SI570_CLK_P
SI570_CLK_N
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations

Attach the GTH Quad Connector

Attach the Samtec BullsEye connector to the connector pad for GTH Quad 117
aligning the two indexing pins on the bottom of the connector with the guide holes on the
board. Hold the connector flush with the board and fasten it by tightening the two captive
screws.
X-Ref Target - Figure 1-4
ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
The image in Figure 1-3 is for reference only and might not reflect the current revision of the
CLKOUT1_P
CLKOUT1_N
Figure 1-4: BullsEye Connector Attached to Quad 117
www.xilinx.com
Running the GTH IBERT Demonstration
Figure 1-3 shows the locations of the
CLKOUT2_P CLKOUT3_P
CLKOUT2_N CLKOUT3_N
UG806_c1_04_022411
CLKOUT4_P
CLKOUT4_N
UG725_c1_03_102010
(Figure 1-4),
9