Clock Connections; Voltage Control; 50 Mhz On-Board Oscillator; Auxiliary Clock Oscillator Socket - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

Chapter 3: Clock Sources

Clock Connections

Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the
top of the FPGA. As shown in
an associated DCM.
Table 3-1: Clock Inputs and Associated Global Buffers and DCMs

Voltage Control

The voltage for all I/O pins in FPGA I/O Bank 0 is controlled by jumper JP9.
Consequently, these clock resources are also controlled by jumper JP9. By default, JP9 is set
for 3.3V. The on-board oscillator is a 3.3V device and might not perform as expected when
jumper JP9 is set for 2.5V.

50 MHz On-Board Oscillator

The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator
is accurate to

Auxiliary Clock Oscillator Socket

The provided 8-pin socket accepts clock oscillators that fit the 8-pin DIP footprint. Use this
socket if the FPGA application requires a frequency other than 50 MHz. This socket is
populated with a 66 MHz oscillator. This clock input is used for some of the reference
designs provided with the board. Alternatively, use the FPGA's Digital Clock Manager
(DCM) to generate or synthesize other frequencies from the on-board 50 MHz oscillator.

SMA Clock Input or Output Connector

To provide a clock from an external source, connect the input clock signal to the SMA
connector. The FPGA can also generate a single-ended clock output or other high-speed
signal on the SMA clock connector for an external device.

UCF Constraints

The clock input sources require two different types of constraints. The location constraints
define the I/O pin assignments and I/O standards. The period constraints define the clock
period—and consequently the clock frequency—and the duty cycle of the incoming clock
signal.
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Clock Input FPGA Pin
CLK_50MHZ C9
CLK_AUX
CLK_SMA A10
± ±
2500 Hz or 50 ppm.
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
Table 3-1, each of the clock inputs also optimally connects to
Global Buffer
GCLK10
B8 GCLK8
GCLK7
Associated DCM
DCM_X0Y1
DCM_X0Y1
DCM_X1Y1
UG257 (v1.1) December 5, 2007
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