Xilinx ML52 Series User Manual
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Xilinx ML52 Series User Manual

Xilinx ML52 Series User Manual

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  • Page 1 With the principle of “Quality Parts,Customers Priority,Honest Operation,and Considerate Service”,our business mainly focus on the distribution of electronic components. Line cards we deal with include Microchip,ALPS,ROHM,Xilinx,Pulse,ON,Everlight and Freescale. Main products comprise IC,Modules,Potentiometer,IC Socket,Relay,Connector.Our parts cover such applications as commercial,industrial, and automotives areas.
  • Page 2 ML52 x User Guide Virtex-5 FPGA RocketIO Characterization Platform UG225 (v2.1) August 4, 2010 0402527-03...
  • Page 3 Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 4: Table Of Contents

    22. Xilinx Generic Interface (XGI) ........
  • Page 5 ML52 x User Guide UG225 (v2.1) August 4, 2010...

  • Page 6: Preface: About This Guide

    This user guide describes the features and operation of the Virtex -5 FPGA ML52x series of RocketIO™ characterization platforms. Additional Documentation The following documents are also available for download at http://www.xilinx.com/virtex5. • Virtex-5 Family Overview The features and product selection of the Virtex-5 family are outlined in this overview. •...

  • Page 7: Additional Support Resources

    PCB and interface level. Additional Support Resources To search the database of silicon and software questions and answers, or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support. www.xilinx.com ML52 x User Guide UG225 (v2.1) August 4, 2010...

  • Page 8: Typographical Conventions

    The address (F) is asserted after Emphasis in text clock event 2. Underlined Text Indicates a link to a web page. http://www.xilinx.com/virtex5 Online Document This document uses the following conventions. An example illustrates each convention. Convention Meaning or Use Example See the section “Additional...
  • Page 9 Preface: About This Guide www.xilinx.com ML52 x User Guide UG225 (v2.1) August 4, 2010...

  • Page 10: Ml52X User Guide

    Power supply brick • SMA wrench Additional Information For current information about the ML52x RocketIO characterization platform, visit www.xilinx.com/ml52x The information includes: • Current version of this user guide in PDF format • Example design files for demonstration of Virtex-5 FPGA features and technology •...

  • Page 11: Related Documents

    Related Documents Related Documents Prior to using the ML52x platforms, users should be familiar with Xilinx resources. See “References,” page 35 for direct links to Xilinx and other related documentation. See the following locations for additional documentation on Xilinx tools and solutions.
  • Page 12 8 Differential Clocks = 16 SMAs in FF1136 24 Transceivers = 96 SMAs in FF1738 12 Differential Clocks = 24 SMAs in FF1738 UG225_01_032608 Figure 1: Virtex-5 FPGA ML52x Platform Block Diagram ML52 x User Guide www.xilinx.com UG225 (v2.1) August 4, 2010...

  • Page 13: Detailed Description

    Each feature is detailed in the numbered sections that follow. Note: The image might not reflect the current revision of the board. X-Ref Target - Figure 2 UG225_02_100206 Figure 2: Detailed Description of Virtex-5 FPGA ML52x Platform Components www.xilinx.com ML52 x User Guide UG225 (v2.1) August 4, 2010...

  • Page 14: Power Switch

    Core voltage for the FPGA (DUT). Max current rating: VCCINT 7.0A / 30.0A 1.0V J101 J112 • ML521 and ML523 boards rated at 7A • ML525 board rated at 30A ML52 x User Guide www.xilinx.com UG225 (v2.1) August 4, 2010...
  • Page 15 AVCCPLL AVTTTX AVTTRX NOTE: The GTP/GTX transceiver power supply names might have the prefix MGT in other Xilinx documentation. Names with and without the MGT prefix are synonymous to each other. UG225_03_100207 Figure 3: Power Supply Block Diagram Power Supply Module...

  • Page 16: Fpga Configuration

    J106 transceiver receiver. Notes: 1. The GTP/GTX transceiver power supply names might have the prefix MGT in other Xilinx documentation. Names with and without the MGT prefix are synonymous to each other. 3. FPGA Configuration The FPGA can only be configured in JTAG mode using one of the following options: •...

  • Page 17: System Ace Controller

    The user may also drive the DUT JTAG interface directly from these headers by attaching the flying wire JTAG cable to pin one of each header. Table 5: JTAG Isolation Jumpers Ref Des Pin Name J128 J129 J131 J132 www.xilinx.com ML52 x User Guide UG225 (v2.1) August 4, 2010...

  • Page 18: System Ace Mpu Port

    Table 6: System ACE Port Connections Pin Name ML521 ML523 ML525 MPA00 MPA01 MPA02 MPA03 MPA04 MPA05 MPA06 MPD00 MPD01 MPD02 MPD03 MPD04 MPD05 MPD06 MPD07 MPIRQ MPBRDY MPCE# MPOE# MPWE# ML52 x User Guide www.xilinx.com UG225 (v2.1) August 4, 2010...

  • Page 19: Oscillator Sockets

    Table Table 9: Differential SMA clock connections Ref Des Pin Name ML521 ML523 ML525 J120 CLK_DIFF_A_P J125 CLK_DIFF_A_N J121 CLK_DIFF_B_P AC12 AH15 AM16 J122 CLK_DIFF_B_N AC13 AG15 AM17 www.xilinx.com ML52 x User Guide UG225 (v2.1) August 4, 2010...

  • Page 20: User Leds (Active-High)

    AE27 AH36 DS25 LED15 AE26 AJ36 DS26 LED14 AF25 AN34 DS27 LED13 AF26 AM34 DS28 LED12 AG27 AM36 DS29 LED11 AG26 AN35 DS30 LED10 AF24 AP35 DS31 LED9 AG25 AN36 ML52 x User Guide www.xilinx.com UG225 (v2.1) August 4, 2010...

  • Page 21: User Dip Switches (Active-High)

    I/O pins on the DUT. These switches can be used for any purpose that the user sees fit. Table 14: User Pushbutton Switches Ref Des Switch ML521 ML523 ML525 PB_SW4 AA12 AF14 AM13 PB_SW3 AA18 AE22 AL30 PB_SW2 AE23 AM29 PB_SW1 AA10 AF13 AK15 www.xilinx.com ML52 x User Guide UG225 (v2.1) August 4, 2010...

  • Page 22: Ddr2 Memory

    For more information on the DDR2 memory devices refer to the Micron DDR2 SDRAM data sheet [Ref Table 15: DDR2 Connections to the DUT Pin Name ML521 ML523 ML525 AF18 AE31 AH39 AC26 AB34 CAS# CK0N CK0P CK1N CK1P AD19 AB30 AV40 ML52 x User Guide www.xilinx.com UG225 (v2.1) August 4, 2010...
  • Page 23 Detailed Description Table 15: DDR2 Connections to the DUT (Cont’d) Pin Name ML521 ML523 ML525 AA36 AA35 AA34 AF15 AF29 AN39 AE13 AH30 AM38 AF13 AJ30 AN38 www.xilinx.com ML52 x User Guide UG225 (v2.1) August 4, 2010...
  • Page 24 AE15 AK31 AM39 AD15 AJ31 AL39 AF14 AF30 AP38 AA32 AF24 AD37 AF25 AD36 AF23 AE37 AD23 AE38 AE22 AE39 AC23 AG38 AC24 AF39 AB22 AF37 DQM0 DQM1 DQM2 DQM3 ML52 x User Guide www.xilinx.com UG225 (v2.1) August 4, 2010...
  • Page 25 DQS3 DQS3# DQS4 AF22 AN40 DQS4# AE21 AP40 DQS5 AC21 AA29 AT39 DQS5# AD21 AA30 AR39 DQS6 DQS6# DQS7 AF20 AB31 AR40 DQS7# AE20 AA31 AT40 RAS# AD20 AC30 AU39 www.xilinx.com ML52 x User Guide UG225 (v2.1) August 4, 2010...

  • Page 26: Gtp/Gtx Transceiver Clock Input Smas

    J166 REFCLKP_134 AW15 Notes: 1. The GTP/GTX transceiver clock pin names might have the prefix MGT in other Xilinx documentation. Names with and without the MGT prefix are synonymous to each other. ML52 x User Guide www.xilinx.com UG225 (v2.1) August 4, 2010...

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