Spi Loader; Spi 8-Bit Data Stream - Texas Instruments Concerto F28M35 Series Technical Reference Manual

C-Boot ROM Description
6.6.14.5 C-Boot ROM SPI_Boot Mode
The SPI loader expects an SPI-compatible 16-bit or 24-bit addressable serial EEPROM or serial flash
device to be present on the SPI-A pins as indicated in
data stream. It does not support a 16-bit data stream.
The SPI-A loader uses following pins:
• SPISIMOA on GPIO16
• SPISOMIA on GPIO17
• SPICLKA on GPIO18
• SPISTEA on GPIO19
The SPI boot ROM loader initializes the SPI module to interface to a serial SPI EEPROM or flash. Devices
of this type include, but are not limited to, the Xicor X25320 (4Kx8) and Xicor X25256 (32Kx8) SPI serial
SPI EEPROMs and the Atmel AT25F1024A serial flash.
The SPI boot ROM loader initializes the SPI with the following settings: FIFO enabled, 8-bit character,
internal SPICLK master mode and talk mode, clock phase = 1, polarity = 0, using the slowest baud rate.
If the download is to be performed from an SPI port on another device, then that device must be setup to
operate in the slave mode and mimic a serial SPI EEPROM. Immediately after entering the SPI_Boot
function, the pin functions for the SPI pins are set to primary and the SPI is initialized. The initialization is
done at the slowest speed possible. Once the SPI is initialized and the key value read, you could specify a
change in baud rate or low speed peripheral clock.
Byte
1
2
3
4
5
6
...
...
17
18
19
20
21
22
...
...
...
604
ROM Code and Peripheral Booting
Figure 6-21. SPI Loader
SPISIMOA
SPISOMIA
Control
subsystem
SPICLKA
SPIESTEA
Table 6-28. SPI 8-Bit Data Stream
Contents
LSB: AA (KeyValue for memory width = 8-bits)
MSB: 08h (KeyValue for memory width = 8-bits)
LSB: LOSPCP
MSB: SPIBRR
LSB: reserved for future use
MSB: reserved for future use
...
Data for this section.
...
LSB: reserved for future use
MSB: reserved for future use
LSB: Upper half (MSW) of Entry point PC[23:16]
MSB: Upper half (MSW) of Entry point PC[31:24] (Note: Always 0x00)
LSB: Lower half (LSW) of Entry point PC[7:0]
MSB: Lower half (LSW) of Entry point PC[15:8]
....
Data for this section.
...
Blocks of data in the format size/destination address/data as shown in the generic
data stream description
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 6-21. The SPI bootloader supports an 8-bit
Serial SPI
EEPROM
DIN
DOUT
CLK
CS
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
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