Input/Output Pins; Clock Sources - Epson S1C17W12 Technical Manual

CLG
X'tal1
OSC1
OSC2
OSC3
R X'tal3/Ceramic3
CR3
OSC4
EXOSC
FOUT

2.3.2 Input/Output Pins

Table 2.3.2.1 lists the CLG pins.
Pin name I/O*
OSC1 A
OSC2 A
OSC3 A
OSC4 A
EXOSC I
FOUT O
If the port is shared with the CLG input/output function and other functions, the CLG function must be assigned to
the port. For more information, refer to the "I/O Ports" chapter.

2.3.3 Clock Sources

IOSC oscillator circuit
The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1
shows the configuration of the IOSC oscillator circuit.
The IOSC oscillator circuit output clock IOSCCLK is used as SYSCLK at booting. The IOSC oscillator circuit
is equipped with an auto-trimming function that automatically adjusts the frequency. This helps reduce fre-
quency deviation due to unevenness in manufacturing quality, temperature, and changes in voltage. For more
information on the auto-trimming function and the oscillation characteristics, refer to "IOSC oscillation auto-
trimming function" in this chapter and "IOSC oscillator circuit characteristics" in the "Electrical Characteris-
tics" chapter, respectively.
S1C17W12/W13 TECHNICAL MANUAL
(Rev. 1.2)
IOSCEN
IOSC
IOSCCLK
oscillator Divider
circuit
OSC1EN
OSC1
OSC1CLK
oscillator Divider
circuit
OSC3EN
OSC3
OSC3CLK
oscillator Divider
circuit
EXOSCEN
EXOSC
EXOSCCLK
clock input
circuit
FOUTEN
FOUT
output
circuit
FOUTDIV[2:0]
Figure 2.3.1.1 CLG Configuration
Table 2.3.2.1 List of CLG Pins
Initial status*
– OSC1 oscillator circuit input
– OSC1 oscillator circuit output
– OSC3 oscillator circuit input
– OSC3 oscillator circuit output
I EXOSC clock input
O (L) FOUT clock output
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
CLKSRC[1:0]
CLKDIV[1:0]
WUPSRC[1:0]
WUPDIV[1:0]
WUPMD
System
Clock
clock
selector
controller
SLEEP, WAKE-UP
Clock
selector
Clock
selector
Function
* Indicates the status when the pin is configured for CLG.
SYSCLK
To CPU and bus
Peripheral circuit 1
CLKSRC[x:0]
CLKDIV[x:0]
Peripheral circuit n
CLKSRC[x:0]
CLKDIV[x:0]
2-7