Input/Output Pins; Clock Sources - Epson S1C31W65 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS

2.3.2 Input/Output Pins

Table 2.3.2.1 lists the CLG pins.
Pin name I/O*
OSC1 A
OSC2 A
OSC3 A
OSC4 A
EXOSC I
FOUT O
If the port is shared with the CLG input/output function and other functions, the CLG function must be assigned to
the port. For more information, refer to the "I/O Ports" chapter.

2.3.3 Clock Sources

IOSC oscillator circuit
The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1
shows the configuration of the IOSC oscillator circuit.
OSC1
OSC1CLK
oscillator
circuit
The IOSC oscillator circuit output clock IOSCCLK is used as SYSCLK at booting. The IOSCCLK frequency
can be selected using the CLGIOSC.IOSCFQ[2:0] bits. The IOSC oscillator circuit is equipped with an auto-
trimming function that automatically adjusts the frequency. This helps reduce frequency deviation due to
unevenness in manufacturing quality, temperature, and changes in voltage. For more information on the auto-
trimming function and the oscillation characteristics, refer to "IOSC oscillation auto-trimming function" in this
chapter and "IOSC oscillator circuit characteristics" in the "Electrical Characteristics" chapter, respectively.
2-8
Table 2.3.2.1 List of CLG Pins
Initial status*
– OSC1 oscillator circuit input
– OSC1 oscillator circuit output
– OSC3 oscillator circuit input
– OSC3 oscillator circuit output
I EXOSC clock input
O (L) FOUT clock output
IOSC oscillator circuit
IOSCEN
IOSCHSAJ[6:0]
Clock IOSCLSAJ[5:0]
oscillator
IOSCFQ[2:0]
IOSCSTAIE
Auto-
IOSCTEDIE
trimming
IOSCTERIE
circuit
IOSCSTM
Figure 2.3.3.1 IOSC Oscillator Circuit Configuration
Seiko Epson Corporation
Function
* Indicates the status when the pin is configured for CLG.
IOSCWT[1:0]
Oscillation
stabilization
waiting circuit
IOSCSTAIF
Interrupt IOSCTEDIF
control circuit IOSCTERIF
IOSCCLK
CPU
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)