Marantz SR5006 Service Manual page 148

LAN8700-AEZG-TR (HDMI : IC14)
nINT/TX_ER/TXD4
MDC
CRS/PHYAD4
MDIO
nRST
TX_EN
VDD33
VDD_CORE
SPEED100/PHYAD0
LAN8700-AEZG-TR Block Diagram
MODE0
MODE1
MODE Control
MODE2
nRST
SMI
MII
TXD[0..3]
TX_EN
TX_ER
TX_CLK
RXD[0..3]
RX_DV
RX_ER
RX_CLK
CRS
COL/CRS_DV
MDC
MDIO
1
2
3
USB3300
4
LAN8700/LAN8700I
Hi-Speed USB2
MII/RMII Ethernet PHY
5
ULPI PHY
36 Pin QFN
6
32 Pin QFN
7
GND FLAG
8
9
Auto-
Negotiation
Management
Control
100M Rx
DSP System:
Logic
Clock
Data Recovery
Equalizer
Receive Section
10M Rx
Logic
10M PLL
27 TXD3
26 TXD2
25 VDDIO
24 TXD1
23 TXD0
22 TX_CLK
21 RX_ER/RXD4
20 RX_CLK/REGOFF
19 R X _ D V
10M Tx 10M
Logic Transmitter
Transmit Section
100M Tx 100M
Logic Transmitter
Analog-to-
Digital
100M PLL
Squelch &
Filters
148
HP Auto-MDIX
MDIX
Control
PLL
Interrupt
Generator
PHY
Address
Latches
LED Circuitry
Central
Bias
TXP / TXN
RXP / RXN
XTAL1
XTAL2
nINT
PHYAD[0..4]
SPEED100
LINK
ACTIVITY
FDUPLEX