Logic Analyzer Connector J18 Pin Assignments - Motorola M68MPBF333 User Manual

MEVB SUPPORT INFORMATION
Table 4-11. Logic Analyzer Connector J17 Pin Assignments (continued)
Pin
12
13
14
15
16
17 – 19
20
Table 4-12. Logic Analyzer Connector J18 Pin Assignments
Pin
1 – 4
5
6 – 9
10
4-10
Mnemonic
PCS0 / PERIPHERAL CHIP SELECT 0 – Active-low output
SPI peripheral chip select signal.
SS SLAVE SELECT – Bi-directional, active-low signal that
initiates serial transmission when SPI is in slave mode;
causes mode fault in master mode.
SCK SPI SERIAL CLOCK – In master mode, the clock
signal from the SPI; in slave mode the clock signal to
the SPI.
MOSI MASTER-OUT, SLAVE-IN – Serial output from SPI in
master mode; serial input to SPI in slave mode.
MISO MASTER-IN, SLAVE-OUT – Serial input to SPI in
master mode; serial output from SPI in slave mode.
GND GROUND
SPARE No connection
GND GROUND
Mnemonic
SPARE No connection
VSSA A/D GROUND – A/D ground reference.
AN0 – AN3 ANALOG INPUT 0 –3 – Analog input line to the MCU
device.
VRL VOLTAGE REFERENCE LOW – Input reference
supply voltage (low) line (must set jumper on the MPB).
Signal
Signal
M68MPB333UM/D