Logic Analyzer Connector J14 Pin Assignments - Motorola M68MPBF333 User Manual

MEVB SUPPORT INFORMATION
Table 4-7. Logic Analyzer Connector J13 Pin Assignments (continued)
Pin
16
17 – 19
20
Table 4-8. Logic Analyzer Connector J14 Pin Assignments
Pin
1, 2
3
4
5
6
7
8
9 – 15
16 – 19
20
4-8
Mnemonic
A19 / ADDRESS BUS BIT 19 – One bit of the 24-bit address
bus.
CS6 CHIP SELECT 6 – Output signal that selects peripheral
or memory devices at programmed addresses.
A18 – A16 ADDRESS BUS 18 – 16 – Three bits of the 24-bit
address bus.
GND GROUND
Mnemonic
SPARE No connection
DSACK0 DATA AND SIZE ACKNOWLEDGE 0 – Active-low
input signal that allows asynchronous data transfers
and dynamic bus sizing between the MCU and external
devices.
MODCLK CLOCK MODE SELECT – Input signal that configures
the MCU internal clock at reset.
TSC THREE STATE CONTROL – When TSC is logic high,
this input signal forces all output drivers to a high-
impedance state.
RESET RESET – Active-low, bi-directional signal to start a
system reset.
RMC READ-MODIFY-WRITE CYCLE – Active-low output
signal that identifies the bus cycle as part of an
indivisible read-modify-write operation.
SPARE No connection
IRQ1 – IRQ7 TARGET INTERRUPT REQUEST 1 – 7 - Active-low
input signals from the target that asynchronously
provides an interrupt priority level to the CPU. IRQ1
has the lowest priority, IRQ7 has the highest.
SPARE No connection
GND GROUND
Signal
Signal
M68MPB333UM/D