Intel Agilex Series Configuration User Manual page 62

Figure 18. Connections for Avalon-ST x16 Single-Device Configuration
Intel ® Agilex ™ Configuration User Guide
62
External Host
CPLD / FPGA
fpga_nconfig
fpga_nstatus
fpga_conf_done
Parallel Flash Loader II IP
or
Microprocessor
or
Custom Logic
fpga_data [15:0]
fpga_valid
fpga_ready
fpga_clk
Non-Volatile Memory Interface
Access Port
External Non-Volatile Memory
.rbf or .pof
V
CCIO_SDM
V
CCIO_SDM
10kΩ
Configuration
10kΩ
Control Signals
(1) (2)
3
MSEL
16
Configuration
Data Signals
External Clock Source (Optional)
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
Intel FPGA
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
MSEL[2:0]
AVST_DATA [15:0]
AVST_VALID
AVST_READY
AVST_CLK
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