Intel CHIPS DKHiQV-AGP User Manual page 23

JP9 1-2
2-3
3-4
1-4
JP10 1-2
2-3
3-4
1-4
JP11 1-2
2-3
3-4
1-4
JP12 1-2
2-3
3-4
1-4
JP13 OPEN
CLOSED
JP15 1-2
OPEN
JP16 1-2
OPEN
JP17 1-2
OPEN
JP18 1-2
OPEN
JP19 1-2
OPEN
JP20 1-2
OPEN
Note: Refer to schematics for additional information.
&+,36
®
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice
DKHiQV-AGP (Fab. Rev. A) User's Guide
JP9/JP10 pin 1 is driven by 32KHZ/GPIO1/GPIO2.
JP9 pin 3 is driven by 32KHZ/GPIO1/CSYNC
JP9 pin 3 is driven by ENABKL/GPIO1/CSYNC
JP9/JP10 pin 1 is driven by ENABKL/GPIO1/CSYNC
JP9/JP10 pin 1 is driven by 32KHZ/GPIO1/GPIO2.
32 KHz oscillator drives 32KHZ/GPIO1/GPIO2 signal
(NOT VALID)
JP9/JP10 pin 1 is driven by 54GPIO2
ENAVEE panel voltage control is driven by ENABKL/GPIO1/CSYNC
ENABKL panel control is driven by ENABKL/GPIO1/CSYNC
ENABKL panel control is driven by ENAVEE/ENABKL
ENAVEE panel voltage control is driven ENAVEE/ENABKL
CSYNC for TV Out is driven by ENABKL/GPIO/CSYNC.
Activity LED is driven by ENABKL/GPIO1/CSYNC.
Activity LED is driven by ACTI/GPIO0/CSYNC.
CSYNC for TV Out is drivven by ACTI/GPIO0/CSYNC.
CSYNC for TV out from JP11 or JP12.
CSYNC for TV out from CSYNC/HSYNC.
P34 panel data for 36-bit panels
P35 panel data for 36-bit panels
P32 panel data for 36-bit panels
P30 panel data for 36-bit panels
P33 panel data for 36-bit panels
P31 panel data for 36-bit panels
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Revision 1.0 7/13/98