Marantz SR5012 Service Manual page 65

No. Pin Name I/O Function
CAD0_I2C I Chip Address 0 Pin in I2C Bus serial control mode
CSN I Chip Select Pin in 3-wire serial control mode
15
DIF I Audio Data Format Select in Parallel control mode. "L": 32-bit MSB, "H": 32-bit I2S
(I2C pin = "H") Control Mode Select Pin "L": I2C Bus serial control mode, "H": Parallel control
PS I
mode.
16
CAD0_SPI I (I2C pin = "L") Chip Address 0 Pin in 3-wire serial control mode
Control Mode Select Pin "L": 3-wire serial control mode
17 I2C I
"H": I2C Bus serial control mode or Parallel control mode.
18 AOUTL1P O Lch Positive Analog Output 1 Pin
19 AOUTL1N O Lch Negative Analog Output 1 Pin
20 VREFL1 I Negative Voltage Reference Input Pin, AVSS
21 VREFH1 I Positive Voltage Reference Input Pin, AVDD
22 AOUTR1N O Rch Negative Analog Output 1 Pin
23 AOUTR1P O Rch Positive Analog Output 1 Pin
24 AOUTL2P O Lch Positive Analog Output 2 Pin
25 AOUTL2N O Lch Negative Analog Output 2 Pin
26 VREFL2 I Negative Voltage Reference Input Pin, AVSS
27 VREFH2 I Positive Voltage Reference Input Pin, AVDD
28 AOUTR2N O Rch Negative Analog Output 2 Pin
29 AOUTR2P O Rch Positive Analog Output 2 Pin
30 AVSS - Analog Ground Pin
31 AVDD - Analog Power Supply Pin, 3.0V-5.5V
32 AOUTL3P O Lch Positive Analog Output 3 Pin
33 AOUTL3N O Lch Negative Analog Output 3 Pin
34 VREFH3 I Positive Voltage Reference Input Pin, AVDD
35 VREFL3 I Negative Voltage Reference Input Pin, AVSS
36 AOUTR3N O Rch Negative Analog Output 3 Pin
37 AOUTR3P O Rch Positive Analog Output 3Pin
38 AOUTL4P O Lch Positive Analog Output 4 Pin
39 AOUTL4N O Lch Negative Analog Output 4 Pin
40 VREFH4 I Positive Voltage Reference Input Pin, AVDD
41 VREFL4 I Negative Voltage Reference Input Pin, AVSS
42 AOUTR4N O Rch Negative Analog Output 4 Pin
43 AOUTR4P O Rch Positive Analog Output 4 Pin
44 LDOE I Internal LDO Enable Pin. "L": Disable, "H": Enable
45 TVDD - Digital Power Supply Pin, 3.0V-3.6V
46 DVSS - Digital Ground Pin
O LDO Output Pin (LDOE pin = "H") This pin should be connected to DVSS with 1.0µF.
47 VDD18
I 1.8V Power Input Pin (LDOE pin = "L")
Power-Down & Reset Pin
48 PDN I When this pin is "L", the AK4458 is powered-down and the control registers are reset to default
state.
Note 2. All input pins except internal pull-up/down pins should not be left floating.
Note 3. PCM mode and DSD mode are controlled by registers. Daisy Chain mode is controlled by both
registers and pins.
Note 4. This pin outputs DVSS when the LDOE pin = "H" and Hi-z when the LDOE pin = "L".
FUNCTIONAL BLOCK DIAGRAM
PD State
Hi-Z
BICK/DCLK
LRCK/DSDL1
Hi-Z
SDTI1/DSDR1
SDTI2/DSDL2
SDTI3/DSDR2/TDMO1
Hi-Z
SDTI4/DSDL3/TDMO2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DSDR3
Hi-Z
DSDL4
Hi-Z DSDR4
Hi-Z
－
－
Hi-Z
Hi-Z
DZF/SMUTE
Hi-Z
CAD1/DCHAIN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
－
I2C
－
CAD0_I2C/CSN/DIF
SCL/CCLK/TDM1
(Note 4)
SDA/CDTI/TDM0
Hi-Z
014011794-E-00
65
4. Block Diagram and Functions
LDOE TVDD VDD18 DVSS PDN AVDD AVSS
Bias
LDO
DATT
8X SCF
Soft Mute
Interpolator
PCM
Data
Interface
Vref
De-empha
DATT Modulator
sis
DSD Filter
Soft Mute
Noise
Rejection
Filter
SCF
DATT
8X SCF
Soft Mute
Interpolator
DSD
Data
Interface
Vref
DATT Modulator
DSD Filter
Soft Mute
Noise
Rejection
Filter
SCF
DATT
8X SCF
Soft Mute
Interpolator
Vref
DATT
Modulator
DSD Filter
Soft Mute
Noise
Rejection
Filter
SCF
DATT 8X
SCF
Soft Mute Interpolator
Vref
DATT Modulator
DSD Filter
Soft Mute
Noise
Rejection
Filter
SCF
Control
Clock
Register
Divider
PS/CAD0_SPI MCLK
Figure 1. Block Diagram
- 5 -
[AK4458]
AOUTL1P
AOUTL1N
VREFH1
VREFL1
AOUTR1P
AOUTR1N
AOUTL2P
AOUTL2N
VREFH2
VREFL2
AOUTR2P
AOUTR2N
AOUTL3P
AOUTL3N
VREFH3
VREFL3
AOUTR3P
AOUTR3N
AOUTL4P
AOUTL4N
VREFH4
VREFL4
AOUTR4P
AOUTR4N
2015/01